US6001414A
Expired / Lapsed
US
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Dual damascene processing method
Assignee: United Microelectronics Corp
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Filing: 1997-12-16
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Granted: 1999-12-14
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Expires: 2017-12-16
Abstract
Abstract A dual damascene processing method comprising the steps depositing sequentially a first oxide layer, a SRO layer and a second oxide layer over a substrate. Then, photolithographic and etching operations are conducted to form a via that links up with a desired wire-connecting region above the substrate. Next, another photolithographic and etching operations are conducted to form interconnect trench lines followed by the deposition of metal into the via and trench. Finally, the surface is polished with a chemical-mechanical polishing operation to remove the unwanted metal on the surface. The invention is capable of controlling the depth of trench and obtaining a smoother trench bottom for the metal lines. Furthermore, the separation of via and trench etching steps makes the control of the final etch profile much easier, thereby able to get an optimal result.
Inventors
- 👤 Yimin Huang
- 👤 Hsiao-Pang Chou
- 👤 Tri-Rung Yew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:32
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/081; H10W20/082; H10W20/084
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
167 words
A dual damascene processing method comprising the steps of: (a) forming a first oxide layer over a substrate having a desired wire-connecting region formed thereon; (b) forming a silicon-rich oxide layer for preventing a parasitic capacitance over the first oxide layer; (c) forming a second oxide layer over the silicon-rich oxide layer; (d) removing portions of the first oxide layer, the silicon-rich oxide layer and the second oxide layer to form a via exposing the desired wire-connecting region; (e) using the silicon-rich oxide layer as a stop layer, subsequently removing portions of the second oxide layer to form at least one interconnect trench line and widening the via in the second oxide layer, the exposed surface of the silicon-rich oxide layer in the via having a smooth sloping edge; and (f) depositing a first metal to fill the via and the interconnect trench line, the first metal directly connecting the desired wire-connecting region through the second oxide layer, the silicon-rich oxide layer and the first oxide layer.
Claim 2
Dependent Claim
167 words
A dual damascene processing method comprising the steps of: (a) forming a first oxide layer over a substrate having a desired wire-connecting region formed thereon; (b) forming a silicon-rich oxide layer for preventing a parasitic capacitance over the first oxide layer; (c) forming a second oxide layer over the silicon-rich oxide layer; (d) removing portions of the first oxide layer, the silicon-rich oxide layer and the second oxide layer to form a via exposing the desired wire-connecting region; (e) using the silicon-rich oxide layer as a stop layer, subsequently removing portions of the second oxide layer to form at least one interconnect trench line and widening the via in the second oxide layer, the exposed surface of the silicon-rich oxide layer in the via having a smooth sloping edge; and (f) depositing a first metal to fill the via and the interconnect trench line, the first metal directly connecting the desired wire-connecting region through the second oxide layer, the silicon-rich oxide layer and the first oxide layer.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein the desired wire-connecting region is a region with a second metal.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein the desired wire-connecting region includes a silicide.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein the silicon-rich oxide layer has a thickness of about 1000 Å to 2000 Å.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein the step of forming the silicon-rich oxide layer includes using plasma-enhanced chemical vapor deposition.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein the trench has a depth equal to the thickness of the second oxide layer.
Claim 8
Dependent Claim
29 words
The method of claim 1, wherein after depositing the first metal into the via and trench, further includes removing the first metal that protrudes above the via and trench.
Claim 9
Dependent Claim
18 words
The method of claim 7, wherein the step of removing the protruded first metal includes using chemical-mechanical polishing.
Claim 10
Dependent Claim
25 words
The method of claim 1, wherein the method further includes repeating the steps on a plurality of conducting layers to form a multi-layered interconnect structure.
Claim 11
Dependent Claim
57 words
The method of claim 1, wherein step (d) further includes the substeps of: forming a photoresist layer over the second oxide layer; patterning with a mask, and then removing portions of the first oxide layer, the silicon-rich oxide layer and the second oxide layer to form via exposing the desired wire-connecting region; and removing the photoresist layer.
Claim 12
Dependent Claim
52 words
The method of claim 1, wherein step (e) further includes the substeps of: forming a photoresist layer over the second oxide layer; patterning with a mask, and using the silicon-rich oxide layer as a stop layer, removing portions of the second oxide layer to form the trench; and removing the photoresist layer.
Claim 13
Dependent Claim
201 words
A dual damascene processing method comprising the steps of: (a) forming a first oxide layer over a substrate having a desired wire-connecting region formed thereon; (b) forming a silicon-rich oxide layer for preventing a parasitic capacitance over the first oxide layer; (c) forming a second oxide layer over the silicon-rich oxide layer; (d) forming a first photoresist layer over the second oxide layer; (e) removing portions of the first oxide layer, the silicon-rich oxide layer and the second oxide layer to form a via exposing the desired wire-connecting region; (f) removing the first photoresist layer; (g) forming a second photoresist layer over the second oxide layer; (h) using the silicon-rich oxide layer as a stop layer, subsequently removing portions of the second oxide layer to form at least one interconnect trench line and widening the via in the second oxide layer, the exposed surface of the silicon-rich oxide layer in the via having a smooth sloping edge; (i) removing the second photoresist layer; and (j) depositing a first metal to fill the via and the interconnect trench line, the first metal directly connecting the desired wire-connecting region through the second oxide layer, the silicon-rich oxide layer and the first oxide layer.
Claim 14
Dependent Claim
201 words
A dual damascene processing method comprising the steps of: (a) forming a first oxide layer over a substrate having a desired wire-connecting region formed thereon; (b) forming a silicon-rich oxide layer for preventing a parasitic capacitance over the first oxide layer; (c) forming a second oxide layer over the silicon-rich oxide layer; (d) forming a first photoresist layer over the second oxide layer; (e) removing portions of the first oxide layer, the silicon-rich oxide layer and the second oxide layer to form a via exposing the desired wire-connecting region; (f) removing the first photoresist layer; (g) forming a second photoresist layer over the second oxide layer; (h) using the silicon-rich oxide layer as a stop layer, subsequently removing portions of the second oxide layer to form at least one interconnect trench line and widening the via in the second oxide layer, the exposed surface of the silicon-rich oxide layer in the via having a smooth sloping edge; (i) removing the second photoresist layer; and (j) depositing a first metal to fill the via and the interconnect trench line, the first metal directly connecting the desired wire-connecting region through the second oxide layer, the silicon-rich oxide layer and the first oxide layer.
Claim 15
Dependent Claim
17 words
The method of claim 12, wherein the desired wire-connecting region is a region with a second metal.
Claim 16
Dependent Claim
13 words
The method of claim 12, wherein the desired wire-connecting region includes a silicide.
Claim 17
Dependent Claim
20 words
The method of claim 12, wherein the silicon-rich oxide layer has a thickness of about 1000 Å to 2000 Å.
Claim 18
Dependent Claim
20 words
The method of claim 12, wherein the step of forming the silicon-rich oxide layer includes using plasma-enhanced chemical vapor deposition.
Claim 19
Dependent Claim
20 words
The method of claim 12, wherein the trench has a depth equal to the thickness of the second oxide layer.
Claim 20
Dependent Claim
29 words
The method of claim 12, wherein after depositing the first metal into the via and trench, further includes removing the first metal that protrudes above the via and trench.
Claim 21
Dependent Claim
18 words
The method of claim 18, wherein the step of removing the protruded first metal includes using chemical-mechanical polishing.
Claim 22
Dependent Claim
25 words
The method of claim 12, wherein the method further includes repeating the steps on a plurality of conducting layers to form a multi-layered interconnect structure.
References Cited (Backward Citations)
US5731242A
Cited
US5382545A
Cited
US5596230A
Cited
US5635423A
Cited
US5705430A
Cited
US5753967A
Cited
US5818110A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-13 | 2003-06-14 | 2003-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-13 | 2007-06-14 | 2007-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-13 | 2011-06-14 | 2011-12-14 | $7700.00 | Window Closed / Lapsed |