Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates

Claim 2

A self contained manufacturing unit for forming Cu interconnect metallurgy on a semiconductor device comprising: an enclosed chamber; an input station for introducing semiconductor wafers to be processed into said chamber; an output station for withdrawing semiconductor wafers that have been processed in said chamber; a Cu plating apparatus station within said chamber; a barrier metal electroless plating apparatus station; a primary polishing apparatus station; a secondary polishing apparatus station; an automated indexer apparatus within said chamber for moving wafers to be processed from said input station, through said Cu plating station, said primary polishing station, said secondary polishing station, said barrier metal etch station, to said output station for withdrawal from said chamber for further processing in associated semiconductor manufacturing apparatus that require high clean room environments.

Claim 3

The self contained unit of claim 1 which further includes a wafer cleaning station within said chamber, said automated indexer apparatus capable of also delivering wafers to be processed to said wafer cleaning station.

Claim 4

The self contained unit of claim 1 wherein said primary polishing apparatus station includes a rotatable platen, a polishing disk on said platen, a means to dispense slurry on said platen, a rotatable carrier above said platen for supporting a wafer to be polished in contact with said polishing disk, said secondary polishing apparatus station including a rotatable platen, a polishing disk on said platen, a rotatable carrier above said platen for supporting a wafer to be cleaned, and a means to dispense water on said platen.

Claim 5

The self contained unit of claim 1 wherein said barrier metal layer plating apparatus station is adapted to electrolessly plate the layer, and said Cu plating apparatus station is adapted to electrolessly plate Cu.

Claim 6

The self contained unit of claim 1 wherein said barrier metal layer plating apparatus is adapted to electrolessly deposit TiW.

Claim 7

A process for forming a Cu interconnect metallurgy on a microminiturized integrated circuit substrate comprising; forming a first dielectric layer on the top surface of said substrate, in a very clean environment; depositing, exposing, and developing a mask on said substrate that defines the desired interconnection metallurgy, in a very clean environment; etching grooves in said first dielectric layer through said mask; removing said mask; depositing a thin first layer of a barrier metal; depositing a thick layer of Cu on the dielectric layer by electro or electroless plating technics, in a less stringent clean environment; mechanically polishing away the thick Cu layer on the surface of the dielectric layer to expose the surface of the barrier layer, in a less stringent clean environment; selectively removing the exposed barrier layer, in a less stringent clean environment; selectively depositing a second thin barrier layer on the surface of the Cu remaining in said grooves, in a less stringent clean environment, forming a second dielectric layer over the first dielectric layer in a very clean environment, and repeating the above steps to form an overlying layer of interconnect metallurgy.

Claim 8

A process for forming a Cu interconnect metallurgy on a microminiturized integrated circuit substrate comprising; forming a first dielectric layer on the top surface of said substrate, in a very clean environment; depositing, exposing, and developing a mask on said substrate that defines the desired interconnection metallurgy, in a very clean environment; etching grooves in said first dielectric layer through said mask; removing said mask; depositing a thin first layer of a barrier metal; depositing a thick layer of Cu on the dielectric layer by electro or electroless plating technics, in a less stringent clean environment; mechanically polishing away the thick Cu layer on the surface of the dielectric layer to expose the surface of the barrier layer, in a less stringent clean environment; selectively removing the exposed barrier layer, in a less stringent clean environment; selectively depositing a second thin barrier layer on the surface of the Cu remaining in said grooves, in a less stringent clean environment, forming a second dielectric layer over the first dielectric layer in a very clean environment, and repeating the above steps to form an overlying layer of interconnect metallurgy.

Claim 9

The process of claim 6 wherein the thick layer of Cu is deposited by electroplating technics using the barrier layer as a conductive base.

Claim 10

The process of claim 6 wherein the barrier layer is activated and the thick layer of Cu is deposited by electroless plating technics.

Claim 11

The process of claim 8 wherein the activation of the barrier layer is achieved with Pd.

Claim 12

The process of claim 6 wherein the second barrier layer is deposited by electroless plating technics, in a less stringent clean environment.

Claim 13

Thee process of claim 6 wherein the grooves are etched in said first dielectric layer using plasma etching technics, in a very clean environment.

Claim 14

The process of claim 11 wherein said thin first barrier layer is TiW deposited by chemical vapor deposition technics, in a very clean environment.

Claim 15

The process of claim 11 wherein said thin first barrier layer is deposited by sputter deposition technics.

Claim 16

The process of claim 7 wherein the masking operation is a two step operation with a first mask to define the via holes, and a second mask to define the interconnection metallurgy pattern.

Claim 17

The process of claim 6 wherein the mechanical polishing is a combination of mechanical and chemical polishing.

Claim 18

The process of claim 6 wherein the barrier layer is TiW.

Claim 19

The process of claim 6 wherein the very clean environment is class 1, and the less stringent clean environment is class 1000.

Claim 20

The process of claim 6 wherein the thick Cu layer is mechanically polished to expose the underlying barrier layer, and the barrier layer is selectively etched away to expose the top surface of said first dielectric layer.

Claim 21

The process of claim 6 wherein the mask operation is a two step operation with a first mask to define the contact holes, and a second mask to define the interconnection metallurgy pattern.