Abstract A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.
A method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprising the steps of: dividing each chip on the wafer into a plurality of regions; determining the metal density for each region of each chip based on the circuit pattern for that region; adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region; forming both the desired circuit pattern and any dummy circuit pattern as openings in a dielectric layer on each chip; coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.
Claim 2
Independent Claim
162 words
A method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprising the steps of: dividing each chip on the wafer into a plurality of regions; determining the metal density for each region of each chip based on the circuit pattern for that region; adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region; forming both the desired circuit pattern and any dummy circuit pattern as openings in a dielectric layer on each chip; coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the maximum metal density is about 60-90%.
Claim 4
Dependent Claim
13 words
The method of claim 2 wherein the minimum metal density is about 20-50%.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein each chip is divided into up to about 1,000 regions.
Claim 6
Dependent Claim
10 words
The method of claim 4 wherein the regions are square.
Claim 7
Dependent Claim
30 words
The method of claim 1 wherein dummy circuit patterns or the setting of a maximum and/or minimum metal density are provided for chip fragments at the edge of the wafer.