Patent US6091122A successfully refreshed from Google Patents.
US6091122A
Expired / Lapsed
US
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Fabrication of mid-cap metal gates compatible with ultra-thin dielectrics
Assignee: GlobalFoundries Inc
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Filing: 1998-02-10
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Granted: 2000-07-18
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Expires: 2018-02-10
Abstract
Abstract A method of fabricating a mid-gap workfunction tungsten gate or W electrode directly onto a gate dielectric material for use in high speed/high density advanced MOS and CMOS devices is provided which utilizes low temperature/low pressure CVD of a tungsten carbonyl. MOS and CMOS devices containing one or more of the CVD W gates or W electrodes manufactured by the present invention are also provided herein.
Inventors
- 👤 Douglas Andrew Buchanan
- 👤 Fenton Read McFeely
- 👤 John Jacob Yurkas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:31
CPC Classifications
C; C23; C23C; C23C16/00; C23C16/06; C23C16/16; H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/60; H10D64/66; H10D64/665; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/42; H10P14/43
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
90 words
A MOS device comprising at least one mid-gap workfunction tungsten (W) gate on an ultra-thin gate dielectric material, said ultra-thin gate dielectric material having a thickness of less than 4.0 nm, wherein said mid-gap W gate is formed by (a) depositing a layer of W onto said ultra-thin gate dielectric material, said ultra-thin gate dielectric material being positioned on a semiconductor substrate and said depositing step being carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a).
Claim 2
Dependent Claim
90 words
A MOS device comprising at least one mid-gap workfunction tungsten (W) gate on an ultra-thin gate dielectric material, said ultra-thin gate dielectric material having a thickness of less than 4.0 nm, wherein said mid-gap W gate is formed by (a) depositing a layer of W onto said ultra-thin gate dielectric material, said ultra-thin gate dielectric material being positioned on a semiconductor substrate and said depositing step being carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a).
Claim 3
Dependent Claim
93 words
A field effect transistor (FET) comprising at least one mid-gap work function tungsten (W) gate on an ultra-thin gate dielectric material, said ultra-thin gate dielectric material having a thickness of less than 4.0 nm, wherein said mid-gap W gate is formed by (a) depositing a layer of W onto said ultra-thin gate dielectric material, said ultra-thin gate dielectric material being positioned on a semiconductor substrate and said depositing step being carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a).
Claim 4
Dependent Claim
93 words
A field effect transistor (FET) comprising at least one mid-gap work function tungsten (W) gate on an ultra-thin gate dielectric material, said ultra-thin gate dielectric material having a thickness of less than 4.0 nm, wherein said mid-gap W gate is formed by (a) depositing a layer of W onto said ultra-thin gate dielectric material, said ultra-thin gate dielectric material being positioned on a semiconductor substrate and said depositing step being carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a).
Claim 5
Dependent Claim
36 words
The MOS device of claim 1 wherein said ultra-thin gate dielectric material is selected from the group consisting of SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof.
Claim 6
Dependent Claim
15 words
The MOS device of claim 3 wherein said ultra-thin gate dielectric is SiO 2 .
Claim 7
Dependent Claim
21 words
The MOS device of claim 1 wherein said semiconductor substrate contains at least one source and at least one drain region.
Claim 8
Dependent Claim
18 words
The MOS device of claim 5 wherein said semiconductor substrate is of the p-type or of the n-type.
Claim 9
Dependent Claim
19 words
The MOS device of claim 6 wherein said semiconductor substrate is a substrate composed of silicon, SiGe or GaAs.
Claim 10
Dependent Claim
14 words
The MOS device of claim 7 wherein said semiconductor substrate is composed of silicon.
Claim 11
Dependent Claim
36 words
The FET device of claim 2 wherein said ultra-thin gate dielectric material is selected from the group consisting of SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof.
Claim 12
Dependent Claim
15 words
The FET device of claim 9 wherein said ultra-thin gate dielectric is SiO 2 .
Claim 13
Dependent Claim
21 words
The FET device of claim 2 wherein said semiconductor substrate contains at least one source and at least one drain region.
Claim 14
Dependent Claim
18 words
The FET device of claim 11 wherein said semiconductor substrate is of the p-type or of the n-type.
Claim 15
Dependent Claim
19 words
The FET device of claim 12 wherein said semiconductor substrate is a substrate composed of silicon, SiGe or GaAs.
Claim 16
Dependent Claim
14 words
The FET device of claim 13 wherein said semiconductor substrate is composed of silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |