US4811066A
Expired / Lapsed
US
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Compact multi-state ROM cell
Assignee: Motorola Solutions Inc
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Filing: 1987-10-19
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Granted: 1989-03-07
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Expires: 2007-10-19
Abstract
Abstract A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V T ), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).
Inventors
- 👤 James R. Pfiester
- 👤 Frank K. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:37
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/671; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
115 words
An insulated gate field effect transistor (IGFET) comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; a gate electrode of semiconductor material overlying the thin dielectric layer and the channel wherein the gate electrode comprises ohmically connected central, first edge, and second edge regions each traversing the entire channel length between the source and drain and with the first and second edge regions of opposite conductivity type to the central region.
Claim 2
Dependent Claim
115 words
An insulated gate field effect transistor (IGFET) comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; a gate electrode of semiconductor material overlying the thin dielectric layer and the channel wherein the gate electrode comprises ohmically connected central, first edge, and second edge regions each traversing the entire channel length between the source and drain and with the first and second edge regions of opposite conductivity type to the central region.
Claim 3
Dependent Claim
31 words
The IGFET of claim 1 wherein the first and second edge regions of the gate are of the first conductivity type and the central region is of the second conductivity type.
Claim 4
Dependent Claim
18 words
The IGFET of claim 1 wherein the regions of the gate are strapped together by a conductive material.
Claim 5
Dependent Claim
14 words
The IGFET of claim 3 wherein the conductive material is a refractory metal silicide.
Claim 6
Dependent Claim
128 words
A compact, multi-state read-only-memory (ROM) cell comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; and a gate of semiconductor material overlying the thin dielectric layer and the channel wherein the gate comprises a central region and first and second edge regions on either side of the central region extending the entire channel length between the source and the drain, wherein the first and second edge regions are of a different conductivity than the central region, and wherein the gate regions are electrically connected.
Claim 7
Dependent Claim
128 words
A compact, multi-state read-only-memory (ROM) cell comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; and a gate of semiconductor material overlying the thin dielectric layer and the channel wherein the gate comprises a central region and first and second edge regions on either side of the central region extending the entire channel length between the source and the drain, wherein the first and second edge regions are of a different conductivity than the central region, and wherein the gate regions are electrically connected.
Claim 8
Dependent Claim
34 words
The compact, multi-state ROM cell of claim 5 wherein the first and second edge regions of the gate are of the first conductivity type and the central region is of the second conductivity type.
Claim 9
Dependent Claim
21 words
The compact, multi-state ROM cell of claim 5 wherein the regions of the gate are strapped together by a conductive material.
Claim 10
Dependent Claim
17 words
The compact, multi-state ROM cell of claim 7 wherein the conductive material is a refractory metal silicide.
Claim 11
Dependent Claim
17 words
The compact, multi-state ROM cell of claim 5 wherein the cell has at least two on states.
Claim 12
Dependent Claim
145 words
A compact, multi-state read-only-memory (ROM) cell comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; a gate of semiconductor material overlying the thin dielectric layer and the channel wherein the gate comprises a central region and first and second edge regions on either side of the central region extending the entire channel length between the source and the drain, wherein the central region is of the second conductivity type and the first and second edge regions are of the first conductivity type; and a refractory metal silicide strap on the gate ohmically interconnecting the central and edge portions of the gate.
Claim 13
Dependent Claim
145 words
A compact, multi-state read-only-memory (ROM) cell comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region in the semiconductor substrate, the source and drain regions being of a second conductivity type and separated by a channel in the semiconductor substrate; a thin dielectric layer on the semiconductor substrate overlying at least the channel; a gate of semiconductor material overlying the thin dielectric layer and the channel wherein the gate comprises a central region and first and second edge regions on either side of the central region extending the entire channel length between the source and the drain, wherein the central region is of the second conductivity type and the first and second edge regions are of the first conductivity type; and a refractory metal silicide strap on the gate ohmically interconnecting the central and edge portions of the gate.
Claim 14
Dependent Claim
17 words
The compact, multi-state ROM cell of claim 10 wherein the cell has at least two on states.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |