Patent US2635615A successfully refreshed from Google Patents.
← Back to Patent Explorer
US6090697A Expired / Lapsed US ⏱️ 0.0 years remaining

Etchstop for integrated circuits

Assignee: Texas Instruments Inc
•
Filing: 1998-06-26
•
Granted: 2000-07-18
•
Expires: 2018-06-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A high-selectivity via etching process. The process includes the steps of: forming an etchstop layer 840 of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; forming a dielectric layer over the etchstop layer; and etching the dielectric layer with a fluorine-bearing etchant.

Inventors

  • 👤 Guoqiang Xing
  • 👤 Glenn A. Cerny
  • 👤 Mark R. Visokay

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 03:34
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/692; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/28; H10P50/282; H10P50/283; H10P50/71; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/046; H10W20/071; H10W20/074; H10W20/076; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10P76/00; H10P76/40; H10P76/405

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 141 words
A method for fabricating an integrated circuit including a plurality of metal layers separated by dielectric layers, said method comprising the steps of: (a) forming a first conductive layer; (b) covering said first conductive layer with a conductive etchstop layer; (c) patterning and etching said etchstop layer in a desired pattern; (d) removing portions of said first metal layer not covered by said patterned etchstop layer; (e) depositing an interlevel dielectric layer on said etchstop layer plus first conductive layer; (f) etching a portion of said interlevel dielectric layer above said etchstop layer plus first conductive layer with an etchant that removes said interlevel dielectric layer at least thirty times faster than said etchstop layer to form a via through said interlevel dielectric layer having a bottom on said etchstop layer; and (g) filling said via with a second conductive layer.
Claim 2
Independent Claim 141 words
A method for fabricating an integrated circuit including a plurality of metal layers separated by dielectric layers, said method comprising the steps of: (a) forming a first conductive layer; (b) covering said first conductive layer with a conductive etchstop layer; (c) patterning and etching said etchstop layer in a desired pattern; (d) removing portions of said first metal layer not covered by said patterned etchstop layer; (e) depositing an interlevel dielectric layer on said etchstop layer plus first conductive layer; (f) etching a portion of said interlevel dielectric layer above said etchstop layer plus first conductive layer with an etchant that removes said interlevel dielectric layer at least thirty times faster than said etchstop layer to form a via through said interlevel dielectric layer having a bottom on said etchstop layer; and (g) filling said via with a second conductive layer.
Claim 3
Dependent Claim 34 words
The method of claim 1, wherein said conductive etchstop layer of step (b) of claim 1 is a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N.
Claim 4
Dependent Claim 10 words
The method of claim 2, wherein said material is Ti--Al--N.
Claim 5
Dependent Claim 25 words
The method of claim 3, wherein said Ti--Al--N is (Ti 1-x Al x )--N, where x is in the range of approximately 0.01 to 0.60.
Claim 6
Dependent Claim 10 words
The method of claim 2, wherein said material is Ti--Al.
Claim 7
Dependent Claim 12 words
The method of claim 5, wherein said material is TiAl 3 .
Claim 8
Dependent Claim 18 words
The method of claim 1, wherein the etchant of step (f) of claim 1 is a fluorine-bearing etchant.
Claim 9
Dependent Claim 22 words
The method of claim 7, wherein said interlevel dielectric is silicon dioxide and said fluorine-bearing etchant is Ar/CF 4 /CHF 3 .
Claim 10
Dependent Claim 22 words
The method of claim 7, wherein said interlevel dielectric is silicon nitride and said fluorine-bearing etchant is Ar/CF 4 /O 2 .
Claim 11
Dependent Claim 51 words
A high-selectivity via etching process, comprising the steps of: (a) forming an etchstop layer of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; (b) forming a dielectric layer over said etchstop layer; and (c) etching said dielectric layer with a fluorine-bearing etchant.
Claim 12
Dependent Claim 51 words
A high-selectivity via etching process, comprising the steps of: (a) forming an etchstop layer of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; (b) forming a dielectric layer over said etchstop layer; and (c) etching said dielectric layer with a fluorine-bearing etchant.
Claim 13
Dependent Claim 10 words
The method of claim 10, wherein said material is Ti--Al--N.
Claim 14
Dependent Claim 25 words
The method of claim 11, wherein said Ti--Al--N is (Ti 1-x Al x )--N, where x is in the range of approximately 0.01 to 0.60.
Claim 15
Dependent Claim 10 words
The method of claim 11, wherein said material is Ti--Al.
Claim 16
Dependent Claim 12 words
The method of claim 13, wherein said material is TiAl 3 .
Claim 17
Dependent Claim 22 words
The method of claim 10, wherein said dielectric layer is silicon dioxide and said fluorine-bearing etchant is Ar/CF 4 /CHF 3 .
Claim 18
Dependent Claim 22 words
The method of claim 10, wherein said dielectric layer is silicon nitride and said fluorine-bearing etchant is Ar/CF 4 /O 2 .

References Cited (Backward Citations)

US4069096A Cited
US4582564A Cited
US5231306A Cited
US5360995A Cited
US5504041A Cited
US5609927A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-07-18 2004-01-17 2004-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-07-18 2008-01-17 2008-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-07-18 2012-01-17 2012-07-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag