US6087210A
Expired / Lapsed
US
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Method of manufacturing a CMOS Transistor
Assignee: SK Hynix Inc
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Filing: 1999-06-04
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Granted: 2000-07-11
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Expires: 2019-06-04
Abstract
Abstract The method of manufacturing a CMOS transistor according to the present invention comprises the steps of forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in the first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of the first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within the first and second regions; forming spacers at said side walls of the gate electrode and the gate oxide film; forming a high concentration implantation region in the first and second regions; and implanting N-type impurity ions into the second region to form a punch stop doping layer below said low concentration impurity implantation region of the second region.
Inventors
- 👤 Yong Sun Sohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:07
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
146 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in said first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of said first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within said first and second regions; forming spacers at the side walls of said gate electrode and the gate oxide film; forming a high concentration implantation region in said first and second regions; and implanting N-type impurity ions into said second region to form a punch stop doping layer below said low concentration impurity implantation region of said second region.
Claim 2
Independent Claim
146 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in said first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of said first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within said first and second regions; forming spacers at the side walls of said gate electrode and the gate oxide film; forming a high concentration implantation region in said first and second regions; and implanting N-type impurity ions into said second region to form a punch stop doping layer below said low concentration impurity implantation region of said second region.
Claim 3
Dependent Claim
31 words
The method of manufacturing a CMOS transistor as claimed in claim 1, wherein said low concentration impurity implantation region is formed by implanting either phosphorous (P) ion or arsenic (As) ion.
Claim 4
Dependent Claim
32 words
The method of manufacturing a CMOS transistor as claimed in claim 2, wherein said phosphorous ion is implanted at a dose of 1.0E12-5E14 ions/cm2 with an energy of less than 20 KeV.
Claim 5
Dependent Claim
32 words
The method of manufacturing a CMOS transistor as claimed in claim 2, wherein said an arsenic ion is implanted at a dose of 1.0E12-5E14 ions/cm2 with an energy of less than 50KeV.
Claim 6
Dependent Claim
37 words
The method of manufacturing a CMOS transistor as claimed in claim 1, wherein said punch stop doping layer is formed by implanting either phosphorous (P) ion or arsenic (As) ion at a at an angle of 30-80°.
Claim 7
Dependent Claim
32 words
The method of manufacturing a CMOS transistor as claimed in claim 5, wherein said phosphorous ion is implanted at a dose of 1.0E12-5E13 ions/cm2 with an energy of 5 through 30 KeV.
Claim 8
Dependent Claim
31 words
The method of manufacturing a CMOS transistor as claimed in claim 5, wherein said arsenic ion is implanted at a dose of 1.0E12-5E-5E13 ions/cm2 with an energy of 10 through 100KeV.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |