US6085325A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for supporting power conservation operation modes
Assignee: Intel Corp
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Filing: 1996-12-16
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Granted: 2000-07-04
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Expires: 2016-12-16
Abstract
Abstract An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.
Inventors
- 👤 David R. Jackson
- 👤 Leonard W. Cross
- 👤 Robert A. Jacobs
- 👤 Ali S. Oztaskin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:56
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F1/04; G06F1/08; G06F1/325; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
141 words
A method performed by a suspend control circuit in a peripheral device, the method comprising: generating an activity signal based on data activity from a host device on a data segment of a bus coupled to the peripheral device; receiving a suspend signal from a microcontroller within the peripheral device in response to a predetermined period of inactivity on the data segment of the bus based on the activity signal; and initiating a suspend procedure to enter a suspend mode based on the suspend signal, the suspend procedure comprising: blocking the activity signal to prevent initiation of a resume procedure during the suspend procedure; storing state information; disabling a clock a first predetermined period of time after initiating the suspend procedure; disabling an oscillator a second predetermined period of time after the clock has been disabled; and un-blocking the activity signal.
Claim 2
Independent Claim
141 words
A method performed by a suspend control circuit in a peripheral device, the method comprising: generating an activity signal based on data activity from a host device on a data segment of a bus coupled to the peripheral device; receiving a suspend signal from a microcontroller within the peripheral device in response to a predetermined period of inactivity on the data segment of the bus based on the activity signal; and initiating a suspend procedure to enter a suspend mode based on the suspend signal, the suspend procedure comprising: blocking the activity signal to prevent initiation of a resume procedure during the suspend procedure; storing state information; disabling a clock a first predetermined period of time after initiating the suspend procedure; disabling an oscillator a second predetermined period of time after the clock has been disabled; and un-blocking the activity signal.
Claim 3
Dependent Claim
51 words
The method of claim 1, further comprising: initiating the resume procedure from the suspend mode based on the activity signal, the resume procedure comprising: enabling the oscillator; enabling the clock a third predetermined period of time after the oscillator has been enabled; and updating the device with the stored state information.
Claim 4
Dependent Claim
24 words
The method of claim 2, wherein the third predetermined period of time is measured by sending a signal through an independent clock reference circuit.
Claim 5
Dependent Claim
20 words
The method of claim 2, wherein the the independent clock reference circuit comprises a resistive-capacitive network having a time constant.
Claim 6
Dependent Claim
186 words
A suspend control circuit in a peripheral device comprising: a bus monitor circuit to monitor a data segment of a bus coupled to the peripheral device for data activity from a host device, said bus monitor to generate an activity signal when data activity is detected; a suspend detect circuit to receive a suspend signal from a microcontroller in the peripheral device in response to a period of inactivity indicated by the activity signal, said suspend detect circuit to initiate a suspend procedure based on the suspend signal to enter a suspend mode; a resume enable circuit to block the activity signal to prevent a resume procedure during the suspend procedure; a time reference circuit to provide a first delay in response to initiation of the suspend procedure for the peripheral device to save state information; a clock enable circuit to disable a clock in the peripheral device after the first delay in response to initiation of the suspend procedure; and an oscillator enable circuit to disable an oscillator in the peripheral device after the clock is disabled in response to initiation of the suspend procedure.
Claim 7
Dependent Claim
186 words
A suspend control circuit in a peripheral device comprising: a bus monitor circuit to monitor a data segment of a bus coupled to the peripheral device for data activity from a host device, said bus monitor to generate an activity signal when data activity is detected; a suspend detect circuit to receive a suspend signal from a microcontroller in the peripheral device in response to a period of inactivity indicated by the activity signal, said suspend detect circuit to initiate a suspend procedure based on the suspend signal to enter a suspend mode; a resume enable circuit to block the activity signal to prevent a resume procedure during the suspend procedure; a time reference circuit to provide a first delay in response to initiation of the suspend procedure for the peripheral device to save state information; a clock enable circuit to disable a clock in the peripheral device after the first delay in response to initiation of the suspend procedure; and an oscillator enable circuit to disable an oscillator in the peripheral device after the clock is disabled in response to initiation of the suspend procedure.
Claim 8
Dependent Claim
52 words
The suspend control circuit of claim 5, further comprising: an interrupt circuit to generate an interrupt signal to the microcontroller after the bus monitor circuit detects activity on the data segment of the bus in the suspend mode, the interrupt signal to signal the microcontroller to configure the peripheral device for operation.
Claim 9
Dependent Claim
81 words
The suspend control circuit of claim 5, wherein the oscillator enable circuit is to enable the oscillator in response to receiving the activity signal and to initiate a resume procedure from the suspend mode; wherein the time reference circuit is to provide a second delay in response to initiation of the resume procedure for the oscillator to stabilize; and wherein the clock enable circuit is to enable the clock after the second delay in response to initiation of the resume procedure.
Claim 10
Dependent Claim
27 words
The suspend control circuit of claim 5, wherein the time reference circuit comprises a resistor-capacitor network that operates in a time-wise independent manner relative to the oscillator.
Claim 11
Dependent Claim
39 words
The suspend control circuit of claim 5, wherein the bus monitor, the suspend detect circuit, the resume enable circuit, the time reference circuit, the oscillator enable circuit, and the clock enable circuit all reside on a same silicon substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |