Synchronized clocking disable and enable circuit

Claim 2

A clocking disable and enable circuit comprising: a multiple stage latching circuit having a latching input and a latching output, said latching circuit is capable of receiving a disable signal at said input and is also capable of delaying said disable signal at said output until said latching circuit receives a clocking signal; and a logic gate having two logic inputs and a single logic output, wherein one logic input is coupled to receive the delayed said disable signal and the other logic input is coupled to receive said clocking signal, said logic output produces a logic output signal synchronized with said clocking signal, and said logic output signal transitions to a steady state voltage at a time in which one input receives a transition of said clocking signal and coincident with a time during which said other input receives the delayed said disable signal, said logic output signal further transitions from said steady state voltage to become synchronized with and equal to said clocking signal at a time in which one input receives a transition of said clocking signal coincident with a time during which said other input ceases receiving the delayed said disable signal.

Claim 3

The clocking circuit as recited in claim 1, wherein said latching circuit comprises at least three latching stages connected in series, wherein each latching stage includes a selectively conductive path connected in series with a latch.

Claim 4

The clocking circuit as recited in claim 2, wherein said selectively conductive path is regulated upon receiving said clocking signal.

Claim 5

The clocking circuit as recited in claim 1, wherein said logic gate comprises a nand gate and the transition of said clocking signal is from a high voltage level to a low voltage level, wherein said high voltage level is greater than said low voltage level.

Claim 6

The clocking circuit as recited in claim 1, wherein said logic gate comprises a nor gate and the transition of said clocking signal is from a low voltage level to a high voltage level, wherein said high voltage level is greater than said low voltage level.

Claim 7

The clocking circuit as recited in claim 1, wherein said steady state output signal continues for a duration equal to a set period of multiple half cycles of said clocking signal.

Claim 8

The clocking circuit as recited in claim 1, wherein said steady state output signal occurs completely after a low-to-high voltage transition of one cycle of said clocking signal has occurred.

Claim 9

The clocking circuit as recited in claim 1, wherein said steady state output signal begins completely after a high-to-low voltage transition of one cycle of said clocking signal has occurred.

Claim 10

A carrier signal frequency tracking system with synchronized clocking disable and enable, comprising: an oscillator; a clocking disable and enable circuit having two inputs and an output, wherein one input is coupled to receive a clocking signal from said oscillator and the other input is coupled to receive a disable/enable signal, said clocking disable and enable circuit further includes: a multiple stage latching circuit having a latching input and a latching output, said latching circuit is capable of receiving said disable/enable signal at said input and delaying said disable/enable signal at said output until said latching circuit receives said clocking signal; a logic gate having two logic inputs and a single logic output, wherein one logic input is coupled to receive the delayed said disable/enable signal and the other logic input is coupled to receive said clocking signal, said logic output produces a logic output signal synchronized with said clocking signal and said logic output signal transitions to a steady state voltage at a time in which one input receives a state of said clocking signal which is equivalent to a desired state of the steady state voltage of said logic output signal, and said logic output signal transitions to a steady state voltage coincident with a time during which said other input receives the delayed said disable/enable signal, said logic output signal further transitions from said steady state voltage to become synchronized with said clocking signal at a time in which one input receives a state of said clocking signal which is equivalent to a desired state of the logic output signal synchronized with said clocking signal at a time coincident with a time during which said other input ceases receiving the delayed said disable/enable signal; and a frequency shift detector circuit having two detector inputs and a detector output, wherein said detector output varies in voltage magnitude depending upon the frequency difference between a carrier signal placed on one detector input and said clocking signal sent from said oscillator and placed on the other detector input.

Claim 11

A carrier signal frequency tracking system with synchronized clocking disable and enable, comprising: an oscillator; a clocking disable and enable circuit having two inputs and an output, wherein one input is coupled to receive a clocking signal from said oscillator and the other input is coupled to receive a disable/enable signal, said clocking disable and enable circuit further includes: a multiple stage latching circuit having a latching input and a latching output, said latching circuit is capable of receiving said disable/enable signal at said input and delaying said disable/enable signal at said output until said latching circuit receives said clocking signal; a logic gate having two logic inputs and a single logic output, wherein one logic input is coupled to receive the delayed said disable/enable signal and the other logic input is coupled to receive said clocking signal, said logic output produces a logic output signal synchronized with said clocking signal and said logic output signal transitions to a steady state voltage at a time in which one input receives a state of said clocking signal which is equivalent to a desired state of the steady state voltage of said logic output signal, and said logic output signal transitions to a steady state voltage coincident with a time during which said other input receives the delayed said disable/enable signal, said logic output signal further transitions from said steady state voltage to become synchronized with said clocking signal at a time in which one input receives a state of said clocking signal which is equivalent to a desired state of the logic output signal synchronized with said clocking signal at a time coincident with a time during which said other input ceases receiving the delayed said disable/enable signal; and a frequency shift detector circuit having two detector inputs and a detector output, wherein said detector output varies in voltage magnitude depending upon the frequency difference between a carrier signal placed on one detector input and said clocking signal sent from said oscillator and placed on the other detector input.

Claim 12

The frequency tracking system as recited in claim 9, wherein said oscillator includes an oscillator input for receiving a voltage level and an oscillator output for delivering said clocking signal of varying frequency dependent upon change in said voltage level.

Claim 13

The frequency tracking system as recited in claim 9, wherein said oscillator is a voltage controlled oscillator, said frequency shift detector includes a phase detector.