US4374331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
D-Type flip-flop circuit
Assignee: Azbil Corp
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Filing: 1981-01-22
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Granted: 1983-02-15
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Expires: 2001-01-22
Abstract
Abstract A delay circuit in a conventional D type flip-flop circuit sets a flip-flop to a predetermined logic state in the event of an internal circuit failure.
Inventors
- 👤 Yuji Yamamoto
- 👤 Sei Shiragaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:19
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
174 words
A flip-flop circuit comprising: a first NAND gate having a pair of input terminals and an output terminal; means for coupling an input signal to one of said pair of first NAND gate input terminals; means for coupling a clock signal to the other of said pair of first NAND gate input terminals; a second NAND gate having a pair of input terminals and an output terminal; means for coupling said output terminal of said first NAND gate to one of said pair of second NAND gate input terminals; means for coupling said clock signal to the other of said pair of said second NAND gate input terminals; a non-synchronous flip-flop circuit having a set input terminal and a reset input terminal; means for coupling said output of said first NAND gate to said set input terminal and means for coupling said output of said second NAND gate to said reset input terminal; and a delay circuit connected between the input of said second NAND gate and the output of said first NAND gate.
Claim 2
Dependent Claim
174 words
A flip-flop circuit comprising: a first NAND gate having a pair of input terminals and an output terminal; means for coupling an input signal to one of said pair of first NAND gate input terminals; means for coupling a clock signal to the other of said pair of first NAND gate input terminals; a second NAND gate having a pair of input terminals and an output terminal; means for coupling said output terminal of said first NAND gate to one of said pair of second NAND gate input terminals; means for coupling said clock signal to the other of said pair of said second NAND gate input terminals; a non-synchronous flip-flop circuit having a set input terminal and a reset input terminal; means for coupling said output of said first NAND gate to said set input terminal and means for coupling said output of said second NAND gate to said reset input terminal; and a delay circuit connected between the input of said second NAND gate and the output of said first NAND gate.
Claim 3
Dependent Claim
188 words
A flip-flop circuit comprising: a first NAND gate having a pair of input terminals and an output terminal; means for coupling an input signal to one of said pair of first NAND gate input terminals; means for coupling a clock signal to the other of said pair of first NAND gate input terminals; a second NAND gate having a pair of input terminals and an output terminal; means for coupling said output terminal of said first NAND gate to one of said pair of second NAND gate input terminals; means for coupling said clock signal to the other of said pair of said second NAND gate input terminals; a non-synchronous flip-flop circuit having a set input terminal and a reset input terminal; means for coupling said output of said first NAND gate to said set input terminal and means for coupling said output of said second NAND gate to said reset input terminal; and means for delaying an input signal to said second NAND gate from the output of said first NAND gate with respect to said clock signal input coupled to said second NAND gate input terminal.
Claim 4
Dependent Claim
188 words
A flip-flop circuit comprising: a first NAND gate having a pair of input terminals and an output terminal; means for coupling an input signal to one of said pair of first NAND gate input terminals; means for coupling a clock signal to the other of said pair of first NAND gate input terminals; a second NAND gate having a pair of input terminals and an output terminal; means for coupling said output terminal of said first NAND gate to one of said pair of second NAND gate input terminals; means for coupling said clock signal to the other of said pair of said second NAND gate input terminals; a non-synchronous flip-flop circuit having a set input terminal and a reset input terminal; means for coupling said output of said first NAND gate to said set input terminal and means for coupling said output of said second NAND gate to said reset input terminal; and means for delaying an input signal to said second NAND gate from the output of said first NAND gate with respect to said clock signal input coupled to said second NAND gate input terminal.
References Cited (Backward Citations)
US4001611A
Cited
US4093878A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-14 | 1986-08-16 | 1987-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-14 | 1990-08-16 | 1991-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-14 | 1994-08-16 | 1995-02-15 | $7700.00 | Window Closed / Lapsed |