Patent US6085260A successfully refreshed from Google Patents.
US6085260A
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US
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Method and circuit for multiplexing an input port and an output port of a microprocessor into a single external interface
Assignee: Visteon Global Technologies Inc
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Filing: 1998-06-08
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Granted: 2000-07-04
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Expires: 2018-06-08
Abstract
Abstract A method and circuit interface for multiplexing an input port and an output port of a microprocessor into a single external interface, wherein the input port and the output port never operate at the same time, is normally active upon a battery cycle, includes a resistor network, a level shifter and a power supply. The resistor network is coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface. The level shifter is coupled to the input port and the resistor network for translating the input signal from the resistor network into a second input signal recognizable by the input port. The power supply is coupled to the resistor network and the level shifter for providing power to the input port so as to enable the input port to recognize the second input signal.
Inventors
- 👤 Eric Robert Nelson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:25
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
128 words
A method for multiplexing an input port and an output port of a microprocessor into a single external interface, the microprocessor further including control logic for preventing operation of the input port and the output port at the same time, the method comprising: providing a resistor network coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface; translating the input signal from the resistor network into a second input signal recognizable by the input port; and providing power to the input port so as to enable the input port to recognize the second input signal.
Claim 2
Independent Claim
128 words
A method for multiplexing an input port and an output port of a microprocessor into a single external interface, the microprocessor further including control logic for preventing operation of the input port and the output port at the same time, the method comprising: providing a resistor network coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface; translating the input signal from the resistor network into a second input signal recognizable by the input port; and providing power to the input port so as to enable the input port to recognize the second input signal.
Claim 3
Dependent Claim
17 words
The method as recited in claim 1 wherein providing the resistor network includes providing a voltage divider.
Claim 4
Dependent Claim
27 words
The method as recited in claim 2 further comprising providing a secondary circuit coupled between the voltage divider and the single external interface for reducing electromagnetic interference.
Claim 5
Dependent Claim
17 words
The method as recited in claim 3 wherein the secondary circuit includes a resistor and a capacitor.
Claim 6
Dependent Claim
32 words
The method as recited in claim 4 further comprising providing a second resistor coupled between the output port and the resistor network for preventing power from being supplied to the output port.
Claim 7
Dependent Claim
25 words
The method as recited in claim 1 wherein translating includes ensuring that a full voltage supplied by the power is applied to the input port.
Claim 8
Dependent Claim
155 words
A circuit interface for multiplexing an input port and an output port of a microprocessor into a single external interface, the microprocessor further including control logic for preventing operation of the input port and the output port at the same time, the circuit interface comprising: a resistor network coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface; a level shifter coupled to the input port and the resistor network for translating the input signal from the resistor network into a second input signal recognizable by the input port; and a power supply coupled to the resistor network and the level shifter for providing power to the input port so as to enable the input port to recognize the second input signal.
Claim 9
Dependent Claim
155 words
A circuit interface for multiplexing an input port and an output port of a microprocessor into a single external interface, the microprocessor further including control logic for preventing operation of the input port and the output port at the same time, the circuit interface comprising: a resistor network coupled between the output port and the single external interface for receiving an input signal from the single external interface for receipt by the input port and for receiving an output signal from the output port for receipt by the single external interface; a level shifter coupled to the input port and the resistor network for translating the input signal from the resistor network into a second input signal recognizable by the input port; and a power supply coupled to the resistor network and the level shifter for providing power to the input port so as to enable the input port to recognize the second input signal.
Claim 10
Dependent Claim
16 words
The circuit interface as recited in claim 7 wherein the resistor network is a voltage divider.
Claim 11
Dependent Claim
88 words
The circuit interface as recited in claim 8 wherein the voltage divider includes a first resistor having a corresponding first and second terminal and a second resistor having a corresponding first and second terminal wherein the first terminal of the first resistor is coupled to the power supply, the second terminal of the first resistor is coupled to the first terminal of the second resistor, the output port and the single external interface, and wherein the second terminal of the second resistor is coupled to the level shifter.
Claim 12
Dependent Claim
34 words
The circuit interface as recited in claim 9 wherein the first and second resistors each have an impedance, the impedance of the second resistor being significantly larger than the impedance of the first resistor.
Claim 13
Dependent Claim
31 words
The circuit interface as recited in claim 9 further comprising a secondary circuit coupled between the second terminal of the first resistor and the single external interface for reducing electromagnetic interference.
Claim 14
Dependent Claim
19 words
The circuit interface as recited in claim 11 wherein the secondary circuit includes a third resistor and a capacitor.
Claim 15
Dependent Claim
81 words
The circuit interface as recited in claim 12 wherein the third resistor includes a corresponding first and second terminal and the capacitor includes a corresponding first and second terminal, wherein the first terminal of the third resistor is coupled to the second terminal of the first resistor and the second terminal of the third resistor is coupled to the first terminal of the capacitor and the single external interface, and wherein the second terminal of the capacitor is coupled to ground.
Claim 16
Dependent Claim
67 words
The circuit interface as recited in claim 13 further comprising a fourth resistor for preventing the power supply from being supplied to the output port, the fourth resistor having a corresponding first and second terminal wherein the first terminal of the fourth resistor is coupled to the output port and the second terminal of the fourth resistor is coupled to the second terminal of the first resistor.
Claim 17
Dependent Claim
32 words
The circuit interface as recited in claim 7 wherein the level shifter includes a transistor for ensuring that a full voltage supplied by the power supply is applied to the input port.
Claim 18
Dependent Claim
33 words
The circuit interface as recited in claim 15 further comprising a limiting resistor coupled between the power supply and the level shifter for limiting a current through the transistor to a safe level.
Claim 19
Dependent Claim
43 words
The circuit interface as recited in claim 16 wherein the limiting resistor includes a corresponding first terminal and second terminal wherein the first terminal of the limiting resistor is coupled to the power supply and the second terminal is coupled to the transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |