Time multiplexing address and data on an existing PC parallel port

Claim 3

A method as defined in claim 1 including the further steps of ceasing application of the address data to the computer data bus lines, ceasing the address control signal, applying a data read signal to the multiplexer and to a peripheral device connected to the address output and the data bus output, writing data to the data bus output from the peripheral device, and passing the data from the data bus output to the computer data bus lines.

Claim 4

A method as defined in claim 1 including the further step of ceasing application of address data to the computer data bus lines, ceasing the address control signal, applying computer data to the computer databus, applying a data write signal to the multiplexer and to a peripheral device connected to the address output and the data bus output, and passing the computer data only to the data output as a result thereof.

Claim 7

A bus interface for interconnecting a computer data bus with a peripheral device, comprising a multiplexer having a computer data bus port, a peripheral data bus port and a peripheral address bus port, the multiplexer including means for receiving an address control signal and in response passing data appearing at the computer data bus port to the peripheral address bus port, the multiplexer including means for receiving a write control signal and in response passing data appearing at the computer data bus port to the peripheral data bus port, and the multiplexer including means for receiving a read control signal and in response passing data appearing at the peripheral data bus port to the computer data bus port.

Claim 8

A bus interface for interconnecting a computer data bus with a peripheral device, comprising a multiplexer having a computer data bus port, a peripheral data bus port and a peripheral address bus port, the multiplexer including means for receiving an address control signal and in response passing data appearing at the computer data bus port to the peripheral address bus port, the multiplexer including means for receiving a write control signal and in response passing data appearing at the computer data bus port to the peripheral data bus port, and the multiplexer including means for receiving a read control signal and in response passing data appearing at the peripheral data bus port to the computer data bus port.

Claim 9

A bus interface as defined in claim 5 including means for providing the write control and read control signals to a peripheral device.

Claim 10

A bus interface as defined in claim 5 in which the means for receiving an address control signal and for passing data to the peripheral address bus port is an address latch.

Claim 11

A bus interface as defined in claim 5 in which the means for receiving the read and write control signals and for passing data is comprised of a bidirectional bus driver for passing data in respectively opposite directions depending on whether the read or write control signal is received thereby.

Claim 12

A bus interface as defined in claim 8 in which the means for receiving an address control signal and for passing data to the peripheral address bus port is an address latch.

Claim 13

A bus interface as defined in claim 5, including a computer databus having plural lines, one group thereof for carrying data, and another group thereof for carrying STROBE, INIT, SLIC IN, and ACK signals from a microprocessor, and means for applying the address control signal on the STROBE line, the write control signal on the INIT line, the read control signal on the SLIC IN line, and an interrupt signal from a peripheral device on the ACK line, the group carrying the data being connected to the computer databus port.

Claim 14

A bus interface as defined in claim 9, including a computer databus having plural lines, one group thereof for carrying data, and another group thereof for carrying STROBE, INIT, SLIC IN, and ACK signals from a microprocessor, and means for applying the address control signal on the STROBE line, the write control signal on the INIT line, the read control signal on the SLIC IN line, and an interrupt signal from a peripheral device on the ACK line, the group carrying the data being connected to the address latch and to the bidirectional driver.

Claim 15

A bus interface as defined in claim 5, including plural peripheral devices, each having an address bus port and a databus port, each having a different address, the address bus port of each peripheral device being connected to the peripheral address bus port of the multiplexer, the databus port of each peripheral device being connected to the peripheral databus port of the multiplexer.

Claim 16

A bus interface as defined in claim 11, including plural peripheral devices, each having an address bus port and a databus port, each having a different address, the address bus port of each peripheral device being connected to the peripheral address bus port of the multiplexer, the databus port of each peripheral device being connected to the peripheral databus port of the multiplexer.