Patent JPS568860A successfully refreshed from Google Patents.
US5652870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer having multiplexable input-output port
Assignee: Renesas Design Corp
•
Filing: 1995-04-11
•
Granted: 1997-07-29
•
Expires: 2015-04-11
Abstract
Abstract A microcomputer or a one-chip computer has address pins and data pins provided separately, and when a specified control signal is provided, the address pins act as multiplex pins for address and data signals. Further, a combination of bits for address signals and bits for data signals to be provided to the multiplex pins are changed according to a width of an external bus. For example, the data bits Di are combined with the address bits Ai, as used previously. Further, the data bits Di-1 are combined with the address bits Ai by shifting by one bit with respect to the address bits. One of the two types of the combination can be selected. If the microcomputer has 16-bit address pins, it can be connected to 8-bit memories having independent address and data pins, while it can also be connected to 8-bit peripherals having multiplex pins without using an external circuit for separating address and data signals.
Inventors
- 👤 Takashi Yamasaki
- 👤 Hiroshi Sasahara
- 👤 Tadahiko Komatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
A microcomputer comprising: a central processing unit; an internal bus for address, data and control signals connected to said central processing unit; an input-output port connected to said central processing unit through said internal bus, said input-output port including a first input-output circuit for address and data signals and a second input-output circuit for data signals to be connected to a first external bus and to a second external bus, respectively, said first input-output circuit comprising a controller for providing control signals, and circuit portions for outputting address or data signals when specified signals are received from said controller, wherein an order of the address signals in relation to the counterpart of the data signals to be output by said circuit portions can be changed by said controller.
Claim 2
Dependent Claim
128 words
A microcomputer comprising: a central processing unit; an internal bus for address, data and control signals connected to said central processing unit; an input-output port connected to said central processing unit through said internal bus, said input-output port including a first input-output circuit for address and data signals and a second input-output circuit for data signals to be connected to a first external bus and to a second external bus, respectively, said first input-output circuit comprising a controller for providing control signals, and circuit portions for outputting address or data signals when specified signals are received from said controller, wherein an order of the address signals in relation to the counterpart of the data signals to be output by said circuit portions can be changed by said controller.
Claim 3
Dependent Claim
44 words
The microcomputer according to claim 1, wherein said controller generates the control signals according to a signal for designating multiplexing or non-multiplexing, a timing signal used for multiplexing, a ##EQU2## signal and a signal for designating a bit width of the first external bus.
Claim 4
Dependent Claim
28 words
The microcomputer according to claim 2, wherein said central processing unit has a pin for setting a signal for designating a bit width of the first external bus.
Claim 5
Dependent Claim
62 words
The microcomputer according to claim 1, the circuit portions outputing address or data signals as A i /D i-1 (i=1-8) where A i denotes an i-th bit address signal and D i-1 denotes an (i-1)-th bit data signal when the bit width of the first external bus is the same as the bit number of the data processed by said circuit portions.
Claim 6
Dependent Claim
31 words
The microcomputer according to claim 4, wherein said circuit portions can process a 16-bit data while the first external bus to be connected to said circuit portions is an 16-bit bus.
Claim 7
Dependent Claim
23 words
The microcomputer according to claim 4, wherein zeroth address signal A0 and a byte high enable signal are used as chip select signals.
Claim 8
Dependent Claim
31 words
The microcomputer according to claim 1, wherein said circuit portions can process a 16-bit data while the first external bus to be connected to said circuit portions is an 8-bit bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |