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US6084248A
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Thin film transistor, manufacturing method thereof, and circuit and liquid crystal display device using the thin film transistor
Assignee: BOE Technology Group Co Ltd
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Filing: 1997-06-27
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Granted: 2000-07-04
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Expires: 2017-06-27
Abstract
Abstract A thin film transistor has a structure capable of decreasing deterioration in Vgs-Ids characteristics. The thin film transistor has a source region composed of an N-type impurity-diffused region, a drain region, and a gate electrode, and a channel region formed directly below the gate electrode. To the source region and the drain region are connected a source electrode and a drain electrode, respectively, through a plurality of contact holes. In the channel region are formed a plurality of P-type impurity-diffused regions at constant intervals.
Inventors
- 👤 Satoshi Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6757; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
112 words
A thin film transistor, comprising: a substrate; a gate electrode; a plurality of non-single crystal thin films formed on the substrate which cross the gate electrode; a channel region formed on each of the non-single crystal silicon thin films; and a first region and a second region, the first region and the second region of a first conduction type formed on the non-single crystal silicon thin film, the first region and the second region separated by the channel region, wherein the first region and the second region are connected to common electrodes and wherein the dimension between the outermost sides of the non-single crystal silicon thin films is 50 μm or more.
Claim 2
Dependent Claim
112 words
A thin film transistor, comprising: a substrate; a gate electrode; a plurality of non-single crystal thin films formed on the substrate which cross the gate electrode; a channel region formed on each of the non-single crystal silicon thin films; and a first region and a second region, the first region and the second region of a first conduction type formed on the non-single crystal silicon thin film, the first region and the second region separated by the channel region, wherein the first region and the second region are connected to common electrodes and wherein the dimension between the outermost sides of the non-single crystal silicon thin films is 50 μm or more.
Claim 3
Dependent Claim
26 words
The thin film transistor according to claim 1, wherein the channel width of each of the non-single crystal silicon thin films is 10 μm or less.
Claim 4
Dependent Claim
20 words
The thin film transistor according to claim 1, wherein a length of the channel region is 4 μm or less.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |