US6075832A — Method and apparatus for deskewing clock signals

Claim 1

Independent Claim 127 words

An apparatus for deskewing clock signals in a synchronous digital system, comprising: a phase detection circuit to receive a plurality of clock signals and generate an output based on a phase relationship between the plurality of clock signals; a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals to adjust the one of the plurality of clock signals based on a delay signal; and a controller coupled to the phase detection circuit and the plurality of delay circuits, the controller to receive the output of the phase detection circuit and generate the delay signal, the controller to transmit the delay signal to one of the plurality of delay circuits based on the output of the phase detection circuit.

Claim 2

Independent Claim 127 words

An apparatus for deskewing clock signals in a synchronous digital system, comprising: a phase detection circuit to receive a plurality of clock signals and generate an output based on a phase relationship between the plurality of clock signals; a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals to adjust the one of the plurality of clock signals based on a delay signal; and a controller coupled to the phase detection circuit and the plurality of delay circuits, the controller to receive the output of the phase detection circuit and generate the delay signal, the controller to transmit the delay signal to one of the plurality of delay circuits based on the output of the phase detection circuit.

Claim 3

Dependent Claim 96 words

The apparatus of claim 1, wherein the phase detection circuit comprises: a first delay block to delay a first clock signal by a pre-determined amount; a second delay block to delay a second clock signal by the pre-determined amount; a first phase detector to receive one of the delayed clock signals and one of the undelayed clock signals; and a second phase detector to receive the other of the delayed clock signals and the other of the undelayed clock signals, the phase detectors configured to compare the delayed and undelayed clock signals and generate an output.

Claim 4

Dependent Claim 63 words

The apparatus of claim 2, wherein the output of the phase detectors has three states, wherein the first output state indicates that the first clock signal leads the second clock signal, wherein the second output state indicates that the second clock signal leads the first clock signal, and wherein the third output state indicates that the first and second clock signals are synchronous.

Claim 5

Dependent Claim 31 words

The apparatus of claim 3, wherein the first output state is a binary 10, the second output state is a binary 01, and the third output state is a binary 00.

Claim 6

Dependent Claim 18 words

The apparatus of claim 4, wherein the first and second delay blocks prevent a binary 11 output state.

Claim 7

Dependent Claim 17 words

The apparatus of claim 2, wherein the phase detectors comprise cross coupled logic gates configured as latches.

Claim 8

Dependent Claim 69 words

The apparatus of claim 1, wherein the each of the plurality of delay circuits comprise: a delay line having two inverters coupled in series and a plurality of capacitive loads selectively coupled to outputs of the two inverters; and a delay shift register to receive the delay signal from the controller, the delay shift register to couple or decouple the plurality of capacitive loads based on the delay signal.

Claim 9

Dependent Claim 36 words

The apparatus of claim 7, wherein all of the plurality of capacitive loads are decoupled from any one delay line containing capacitive loads before a different delay line inverter output is coupled to the capacitive load.

Claim 10

Dependent Claim 34 words

The apparatus of claim 7, wherein the controller comprises means for adjusting the delay shift registers based on the output of the phase detection circuit and a current state of the delay shift registers.

Claim 11

Dependent Claim 31 words

The apparatus of claim 1, wherein the controller prevents addition of delay to one of the plurality of clock signals when delay exists on another of the plurality of clock signals.

Claim 12

Dependent Claim 49 words

The apparatus of claim 7, wherein one of the plurality of clock signals is disabled, wherein the controller maintains a current state of the delay shift register of the plurality of delay circuits, and wherein the controller drives the output of the phase detection circuit to a predetermined state.

Claim 13

Dependent Claim 140 words

A synchronous digital system comprising: a clock having a frequency; and a processor comprising: a generator to receive the frequency of the system clock and generate a plurality of clock signals whose fraction synchronize with the system clock; a phase detection circuit to receive the plurality of clock signals and generate an output based on the phase relationship of the plurality of clock signals; a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals to adjust the one of the plurality of clock signals based on a delay signal; and a controller configured to receive the output of the phase detection circuit and generate the delay signal, the controller to transmit the delay signal to one of the plurality of delay circuits based on the output of the phase detection circuit.

Claim 14

Dependent Claim 140 words

A synchronous digital system comprising: a clock having a frequency; and a processor comprising: a generator to receive the frequency of the system clock and generate a plurality of clock signals whose fraction synchronize with the system clock; a phase detection circuit to receive the plurality of clock signals and generate an output based on the phase relationship of the plurality of clock signals; a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals to adjust the one of the plurality of clock signals based on a delay signal; and a controller configured to receive the output of the phase detection circuit and generate the delay signal, the controller to transmit the delay signal to one of the plurality of delay circuits based on the output of the phase detection circuit.

Claim 15

Independent Claim 137 words

An apparatus configured to deskew clock signals, the apparatus comprising: a phase detection circuit to receive a plurality of clock signals and generate data based on a phase relationship between the clock signals; a plurality of registers, each register coupled to a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals, wherein the delay circuit adjusts the delay on one of the plurality of clock signals based on a value stored in the register; and a controller coupled to the phase detection circuit and the plurality of registers, the controller reading the data from the phase detection circuit to determine a delay between the plurality of clock signals, wherein the controller selectively adjusts the delay between the plurality of clock signals using one of the plurality of registers.

Claim 16

Independent Claim 137 words

An apparatus configured to deskew clock signals, the apparatus comprising: a phase detection circuit to receive a plurality of clock signals and generate data based on a phase relationship between the clock signals; a plurality of registers, each register coupled to a plurality of delay circuits, each delay circuit coupled to a corresponding one of the plurality of clock signals, wherein the delay circuit adjusts the delay on one of the plurality of clock signals based on a value stored in the register; and a controller coupled to the phase detection circuit and the plurality of registers, the controller reading the data from the phase detection circuit to determine a delay between the plurality of clock signals, wherein the controller selectively adjusts the delay between the plurality of clock signals using one of the plurality of registers.

Claim 17

Dependent Claim 45 words

The apparatus of claim 13 further configured to deskew clock signals in a digital system having a low power mode, wherein the phase detection data is stored and the controller inserts a predetermined delay on the plurality of clock lines during the low power mode.

Claim 18

Dependent Claim 40 words

The apparatus of claim 14, wherein the controller restores the delay to the plurality of clock signals using the stored phase detection data during a transition from the low power mode to a normal operation mode of the digital system.

Claim 19

Dependent Claim 45 words

The apparatus of claim 13, wherein an output of a register is coupled to the controller, the controller to selectively adjust the delay on one of the plurality of clock signals using the data from the phase detection circuit and the output of the register.

Claim 20

Dependent Claim 20 words

The apparatus of claim 16, wherein the output of the register comprises a single bit value stored in the register.

Claim 21

Dependent Claim 23 words

The apparatus of claim 16, wherein the delay circuit adjusts a delay on a clock line by adding or subtracting a capacitive load.

Claim 22

Independent Claim 153 words

A method of deskewing a digital system, comprising: determining a phase relationship between a plurality of clock signals, each of the plurality of clock signals coupled to a delay circuit, the delay circuit having an output; adjusting at least one of the plurality of clock signals based on the phase relationship and the output of the delay circuit to synchronize the plurality of clock signals; applying the phase relationship to a controller, the controller determining which of the plurality of clock signals requires adjustment based on the phase relationship and the output of the delay circuit; transmitting a controller signal to the delay circuit of one of the plurality of clock signals determined by the controller to require adjustment, the delay circuit coupled to and affecting the delay of one of the plurality of clock signals; and modifying the delay of one of the plurality of clock signals based on the controller signal.

Claim 23

Independent Claim 153 words

A method of deskewing a digital system, comprising: determining a phase relationship between a plurality of clock signals, each of the plurality of clock signals coupled to a delay circuit, the delay circuit having an output; adjusting at least one of the plurality of clock signals based on the phase relationship and the output of the delay circuit to synchronize the plurality of clock signals; applying the phase relationship to a controller, the controller determining which of the plurality of clock signals requires adjustment based on the phase relationship and the output of the delay circuit; transmitting a controller signal to the delay circuit of one of the plurality of clock signals determined by the controller to require adjustment, the delay circuit coupled to and affecting the delay of one of the plurality of clock signals; and modifying the delay of one of the plurality of clock signals based on the controller signal.

Claim 24

Dependent Claim 108 words

The method of claim 19, wherein determining the phase relationship comprises: applying a first clock signal to a first phase detector; delaying a second clock signal by a pre-determined amount; applying the second clock to the first phase detector; applying the second clock signal to a second phase detector; delaying the first clock signal by the pre-determined amount; and applying the first clock signal to the second phase detector, the first and second phase detectors generating the phase relationship corresponding to the first clock signal leading the second clock signal, the second clock signal leading the first clock signal, and the first and second clock signals being synchronous.

Claim 25

Dependent Claim 32 words

The method of claim 20, wherein modifying the delay comprises decreasing the delay of the plurality of clock signals to no delay before increasing the delay of the plurality of clock signals.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-06-13	2003-12-13	2004-06-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-06-13	2007-12-13	2008-06-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-06-13	2011-12-13	2012-06-13	$7700.00	Window Closed / Lapsed

Method and apparatus for deskewing clock signals

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