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US6066560A
Expired / Lapsed
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Non-linear circuit elements on integrated circuits
Assignee: Bell Semiconductor LLC
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Filing: 1998-05-05
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Granted: 2000-05-23
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Expires: 2018-05-05
Abstract
Abstract An electrical interconnection structure on an integrated circuit is provided that has a) a substrate layer; b) a diffusion barrier on the substrate layer; c) a copper layer on the diffusion barrier; and d) a copper oxide layer on the copper layer. Methods of making such an interconnection structure is also provided. Such an interconnection structure may be used as a rectifier to prevent damage of sensitive devices from voltage spikes.
Inventors
- 👤 James P. Yakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:50
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W20/01; H10W20/031; H10W20/056; H10W20/071; H10W20/074; H10W20/076
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
55 words
A method of forming a non-linear circuit element in an integrated circuit, the method comprising forming a trench in a semiconductor substrate; forming a first diffusion barrier along a bottom surface and side surfaces of the trench; at least partially filling the trench with copper; and forming a copper oxide layer on the copper layer.
Claim 2
Independent Claim
55 words
A method of forming a non-linear circuit element in an integrated circuit, the method comprising forming a trench in a semiconductor substrate; forming a first diffusion barrier along a bottom surface and side surfaces of the trench; at least partially filling the trench with copper; and forming a copper oxide layer on the copper layer.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein forming a copper oxide layer includes oxidizing at least a part of the copper layer.
Claim 4
Independent Claim
141 words
A method of forming a non-linear circuit element in an integrated circuit, the method comprising forming a trench in a semiconductor substrate; forming a first diffusion barrier along a button surface and side surface of the trench; at least partially filling the trench with copper; and forming a copper oxide layer on the copper layer, wherein forming a copper oxide layer includes: forming a dielectric layer over the layer of copper and etching through the dielectric layer to expose at least a portion of the copper layer; depositing a second diffusion barrier onto the exposed copper layer and remaining dielectric layer; selectively etching the second diffusion barrier to expose at least a portion of the copper layer, wherein sidewalls of the remaining dielectric layer remain covered by the second diffusion barrier; and providing a copper oxide layer over the exposed copper.
Claim 5
Independent Claim
141 words
A method of forming a non-linear circuit element in an integrated circuit, the method comprising forming a trench in a semiconductor substrate; forming a first diffusion barrier along a button surface and side surface of the trench; at least partially filling the trench with copper; and forming a copper oxide layer on the copper layer, wherein forming a copper oxide layer includes: forming a dielectric layer over the layer of copper and etching through the dielectric layer to expose at least a portion of the copper layer; depositing a second diffusion barrier onto the exposed copper layer and remaining dielectric layer; selectively etching the second diffusion barrier to expose at least a portion of the copper layer, wherein sidewalls of the remaining dielectric layer remain covered by the second diffusion barrier; and providing a copper oxide layer over the exposed copper.
Claim 6
Dependent Claim
15 words
The method of claim 3 further including performing chemical-mechanical planarization of the copper oxide layer.
Claim 7
Dependent Claim
17 words
The method of claim 3 further including performing an anisotropic etch back of the copper oxide layer.
Claim 8
Dependent Claim
32 words
The method of claim 3 wherein the trench is formed by applying a patterned resist, etching the substrate where the resist is not present to form the trench, and removing the resist.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |