Diffusion barrier for electrical interconnects in an integrated circuit

Claim 1

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. forming a capturing layer over the substrate, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; b. forming a blocking layer over the capturing layer, the blocking layer being substantially unreactive with the capturing layer at approximately room temperature and having a thickness in the range of approximately 10 Å to 500 Å; and c. forming a conductive layer directly on the blocking layer, the conductive layer being both thicker than the blocking layer and substantially unreactive with the blocking layer at approximately room temperature, the conductive layer further being substantially reactive with the capturing layer.

Claim 2

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. forming a capturing layer over the substrate, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; b. forming a blocking layer over the capturing layer, the blocking layer being substantially unreactive with the capturing layer at approximately room temperature and having a thickness in the range of approximately 10 Å to 500 Å; and c. forming a conductive layer directly on the blocking layer, the conductive layer being both thicker than the blocking layer and substantially unreactive with the blocking layer at approximately room temperature, the conductive layer further being substantially reactive with the capturing layer.

Claim 11

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. forming an electrically conductive capturing layer over the substrate, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; b. forming an electrically conductive blocking layer over the capturing layer, the blocking layer being both thicker than the capturing layer and substantially unreactive with the capturing layer up to a temperature of approximately 200° C. and having a thickness in the range of approximately 50 Å to 500 Å; and c. forming a copper layer directly on the blocking layer, the copper layer primarily comprising copper, the copper layer being both thicker than the blocking layer and substantially unreactive with the blocking layer up to a temperature of approximately 200° C., the copper layer further being substantially reactive with the capturing layer at a temperature of approximately 200° C.

Claim 12

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. forming an electrically conductive capturing layer over the substrate, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; b. forming an electrically conductive blocking layer over the capturing layer, the blocking layer being both thicker than the capturing layer and substantially unreactive with the capturing layer up to a temperature of approximately 200° C. and having a thickness in the range of approximately 50 Å to 500 Å; and c. forming a copper layer directly on the blocking layer, the copper layer primarily comprising copper, the copper layer being both thicker than the blocking layer and substantially unreactive with the blocking layer up to a temperature of approximately 200° C., the copper layer further being substantially reactive with the capturing layer at a temperature of approximately 200° C.

Claim 18

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. etching a trench in a dielectric material formed over the substrate; b. forming an electrically conductive capturing layer over the dielectric material, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; c. forming an electrically conductive blocking layer over the capturing layer, the blocking layer having a thickness in the range of approximately 50 Å to 500 Å, and being substantially unreactive with the capturing layer up to a temperature of approximately 500° C.; d. forming a copper layer directly on the blocking layer, the copper layer primarily comprising copper, the copper layer being both thicker than the blocking layer and substantially unreactive with the blocking layer up to a temperature of approximately 500° C., the copper layer further being substantially reactive with the capturing layer at a temperature of approximately 200° C.; and e. removing a portion of the copper layer which exists outside the trench using a chemical-mechanical polishing process to substantially isolate the copper layer within the trench.

Claim 19

A method of forming an electrical interconnect over a semiconductor substrate, the method comprising the steps of: a. etching a trench in a dielectric material formed over the substrate; b. forming an electrically conductive capturing layer over the dielectric material, the capturing layer having a thickness in the range of approximately 5 Å to 100 Å; c. forming an electrically conductive blocking layer over the capturing layer, the blocking layer having a thickness in the range of approximately 50 Å to 500 Å, and being substantially unreactive with the capturing layer up to a temperature of approximately 500° C.; d. forming a copper layer directly on the blocking layer, the copper layer primarily comprising copper, the copper layer being both thicker than the blocking layer and substantially unreactive with the blocking layer up to a temperature of approximately 500° C., the copper layer further being substantially reactive with the capturing layer at a temperature of approximately 200° C.; and e. removing a portion of the copper layer which exists outside the trench using a chemical-mechanical polishing process to substantially isolate the copper layer within the trench.