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US6060910A
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Dynamic logic circuit
Assignee: NEC Corp
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Filing: 1998-08-07
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Granted: 2000-05-09
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Expires: 2018-08-07
Abstract
Abstract A high-speed dynamic logic circuit having a high tolerance to noise includes pMOS and nMOS transistors constructing a buffer, which is connected to an internal dynamic node, for driving an output terminal. Only the pMOS transistor, which operates in an evaluation cycle, is connected to the dynamic node. The nMOS transistor is driven by a signal that is the inverse of a precharge signal. A weak latch, or an nMOS transistor of minimum size driven by the dynamic node, is connected to the output terminal as a leakage compensation circuit.
Inventors
- 👤 Shigeto Inui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0966
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
129 words
A dynamic logic circuit comprising: logic generating module which includes: a logic network constructed by a plurality of transistors; a precharge transistor connected between said logic network and a power supply terminal and having a precharge signal input thereto for performing a precharge operation; and a control transistor connected between said logic network and a ground terminal and having the precharge signal input thereto for controlling operation of said logic network; a transistor connected between the power supply terminal and an output terminal for charging the output terminal based upon result of evaluation by said logic generating module; and a transistor connected between the ground terminal and the output terminal and having a signal that is the inverse of the precharge signal input thereto for discharging the output terminal.
Claim 2
Dependent Claim
129 words
A dynamic logic circuit comprising: logic generating module which includes: a logic network constructed by a plurality of transistors; a precharge transistor connected between said logic network and a power supply terminal and having a precharge signal input thereto for performing a precharge operation; and a control transistor connected between said logic network and a ground terminal and having the precharge signal input thereto for controlling operation of said logic network; a transistor connected between the power supply terminal and an output terminal for charging the output terminal based upon result of evaluation by said logic generating module; and a transistor connected between the ground terminal and the output terminal and having a signal that is the inverse of the precharge signal input thereto for discharging the output terminal.
Claim 3
Dependent Claim
51 words
The logic circuit according to claim 1, further comprising a leakage compensation circuit which includes: an inverter having the output terminal connected to its input; and a transistor connected between an output terminal and the ground terminal and having an output of said inverter input thereto for discharging the output terminal.
Claim 4
Dependent Claim
38 words
The logic circuit according to claim 1, further comprising a transistor connected between the output terminal and the ground terminal and having the result of evaluation by said logic generating module input thereto for discharging the output terminal.
Claim 5
Dependent Claim
25 words
The logic circuit according to claim 1, wherein said transistors for charging and discharging the output terminal are pMOS transistor and an nMOS transistor, respectively.
Claim 6
Dependent Claim
21 words
The logic circuit according to claim 1, further comprising a leak compensating circuit connected to an output of said logic network.
Claim 7
Dependent Claim
206 words
A dynamic logic circuit comprising: a logic network constructed by a plurality of transistors; a first transistor connected between said logic network and a power supply terminal on a side of high potential and having a precharge signal input thereto for performing a precharge operation; and a second transistor connected between said logic network and a power supply terminal on a side of low potential and having the precharge signal input thereto for controlling operation of said logic network; wherein an output buffer is provided for outputting, to an output terminal, the value of a node connected to the result of an evaluation by said logic network, said output buffer having a transistor, which is on a side of high potential, that operates in an evaluation cycle, and a transistor on a side of low potential, said transistor on the side of high potential having a gate terminal connected to said node, and said transistor on the side of low potential having a gate terminal connected to a signal that is the inverse of the precharge signal; a latch circuit for latching the state of said output buffer, or a transistor driven by the node, being connected to the output terminal as a leakage compensation circuit.
Claim 8
Dependent Claim
206 words
A dynamic logic circuit comprising: a logic network constructed by a plurality of transistors; a first transistor connected between said logic network and a power supply terminal on a side of high potential and having a precharge signal input thereto for performing a precharge operation; and a second transistor connected between said logic network and a power supply terminal on a side of low potential and having the precharge signal input thereto for controlling operation of said logic network; wherein an output buffer is provided for outputting, to an output terminal, the value of a node connected to the result of an evaluation by said logic network, said output buffer having a transistor, which is on a side of high potential, that operates in an evaluation cycle, and a transistor on a side of low potential, said transistor on the side of high potential having a gate terminal connected to said node, and said transistor on the side of low potential having a gate terminal connected to a signal that is the inverse of the precharge signal; a latch circuit for latching the state of said output buffer, or a transistor driven by the node, being connected to the output terminal as a leakage compensation circuit.
Claim 9
Dependent Claim
42 words
The dynamic logic circuit according to claim 6, wherein said transistor of the output buffer on the side of high potential is a pMOS transistor, and said transistor of the output buffer on the side of low potential is an nMOS transistor.
Claim 10
Dependent Claim
33 words
The dynamic logic circuit according to claim 6, wherein said latch circuit comprises a transistor being connected between the output terminal and the ground terminal and having its gate connected to said node.
Claim 11
Dependent Claim
17 words
The dynamic logic circuit according to claim 8, wherein said latch circuit transistor is an nMOS transistor.
Claim 12
Dependent Claim
22 words
The dynamic logic circuit according to claim 5, further comprising a leak compensating circuit connected to an output of said logic network.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |