US5677641A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
Assignee: Hitachi Ltd
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Filing: 1995-04-18
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Granted: 1997-10-14
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Expires: 2015-04-18
Abstract
Abstract The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
Inventors
- 👤 Yoji Nishio
- 👤 Kosaku Hirose
- 👤 Hideo Hara
- 👤 Katsunori Koike
- 👤 Kayoko Nemoto
- 👤 Tatsumi Yamauchi
- 👤 Fumio Murabayashi
- 👤 Hiromichi Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:00
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
295 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate.
Claim 2
Dependent Claim
295 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate.
Claim 3
Dependent Claim
58 words
A semiconductor integrated circuit device according to claim 1, wherein a domino circuit is configured by multi-stage connection of composite circuits comprising the logic circuits and gate circuits, wherein said clock signals are received by the third field effect transistor and the fifth field effect transistor, and said output is input as input signal for said logic circuit.
Claim 4
Dependent Claim
32 words
A semiconductor integrated circuit device according to claim 1 or 2, wherein the input signal to be input to the gate of the first field effect transistor is input through a bus.
Claim 5
Dependent Claim
318 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate; wherein the input signal to be input to the gate of the first conductivity type field effect transistor is input through a bus.
Claim 6
Dependent Claim
318 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate; wherein the input signal to be input to the gate of the first conductivity type field effect transistor is input through a bus.
Claim 7
Dependent Claim
372 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate; wherein a domino circuit is configured by multi-stage connection of composite circuits comprising the logic circuits and gate circuits, wherein said clock signals are received by the second conductivity type field effect transistor and the fourth conductivity type field effect transistor, said output being input as an input signal for said logic circuit, and wherein the input signal to be input to the gate of the first conductivity type field effect transistor is input through a bus.
Claim 8
Dependent Claim
372 words
A semiconductor integrated circuit device comprising: (1) a logic circuit equipped with at least one field effect transistor to enter at least one signal, to perform a logic operation and to output signals, and (2) a gate circuit comprising: (a) a first field effect transistor of a first conductivity type having a gate, a source, and a drain, wherein a signal from said logic circuit enters the gate as an input signal, the drain is connected to an output of the gate circuit and the source is connected to a first potential; (b) a second field effect transistor of a second conductivity type, opposite to the first conductivity type, having a gate, a drain, and a source, wherein the source is connected to a second potential different from the first potential, and the drain is connected to the said output of the gate circuit; (c) a third field effect transistor of the second conductivity type having a gate, a source, and a drain, wherein a clock signal is input to the gate, the source is connected to the second potential and the drain is connected to the gate of the second field effect transistor; and (d) a fourth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein one of the source or drain is connected to the gate of the first field transistor and the other of the source or drain is connected to the gate of the second field effect transistor; and (3) a fifth field effect transistor of the first conductivity type having a gate, a source, and a drain, wherein the source and drain are connected between the said logic circuit and said first potential, and said clock signal is input to the gate; wherein a domino circuit is configured by multi-stage connection of composite circuits comprising the logic circuits and gate circuits, wherein said clock signals are received by the second conductivity type field effect transistor and the fourth conductivity type field effect transistor, said output being input as an input signal for said logic circuit, and wherein the input signal to be input to the gate of the first conductivity type field effect transistor is input through a bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |