Flip-flop with logic function incorporated therein with minimal time penalty

Claim 2

A circuit configured to operate in a first phase and a second phase, said circuit comprising: a first stage having: a data port wherein said data port is coupled to receive a plurality of data signals; a clock input lead wherein said clock input lead is coupled to receive a clock signal, said first phase occurring when said clock signal has a first logic level and said second phase occurring when said clock signal is has a second logic level; an output lead; a logic block having a second lead coupled to said output lead of said first stage, a plurality of leads coupled to said data port, and a first lead, wherein said logic block is configured to provide a conductive path between said first and second leads of said logic block as a function of a logic state of said plurality of data signals; a shut-off mechanism coupling said output lead of said first stage to said second lead of said logic block, wherein: during said first phase, said first stage is operative to provide at said output lead of said first stage a first phase output signal having a predetermined logic level, and during said second phase, said first stage is operative to provide at said output lead of said first stage a second phase output signal as a function of a logic state of said plurality of data signals received at said data port of said first stage; and a second stage having a first input lead coupled to said output lead of said first stage, a second input lead coupled to said clock input lead of said first stage, and an output lead, wherein: during said first phase, said second stage is operative to maintain at said output lead of said second stage an output signal generated by said second stage prior to said first phase, said second stage maintaining said output signal of said second stage independently of said first phase output signal provided by said first stage during said first phase, and during said second phase, said second stage is operative to provide at said output lead of said second stage an output signal as a function of a logic level of said second phase output signal of said first stage and further wherein said shut-off mechanism maintains said predetermined logic level at said output lead of said first stage throughout said second phase in response to said second phase output signal of said first stage having a logic level equivalent to said predetermined logic level throughout a shut-off delay, said shut-off delay having a predetermined time period starting when said second phase starts.

Claim 3

The circuit of claim 1 wherein said first stage further comprises: a switch having a first terminal coupled to a first voltage source, a second terminal coupled to said clock input lead of said first stage, and a third terminal coupled to said first lead of said logic block, wherein said switch is configured to provide a conductive path between said first terminal and said third terminal during said second phase.

Claim 4

The circuit of claim 1, wherein, during said second phase, said shut-off mechanism is configured to provide a conductive path between said output lead of said first stage and second lead of said logic block when said second phase output signal of said first stage has a logic level different from said predetermined logic level and to open-circuit said conductive path when said second phase output signal of said first stage has a logic level equivalent to said predetermined logic level.

Claim 5

The circuit of claim 2, wherein said shut-off mechanism comprises: a first transistor having a first lead coupled to said output lead of said first stage, a second lead coupled to said second lead of said logic block, and a third lead; a first inverter having an input lead coupled to said clock input lead of said first stage; a second inverter having an input lead coupled to an output lead of said first inverter; and a logic gate having a first input lead coupled to said output lead of said first stage, a second input lead coupled to an output lead of said second inverter, and an output lead coupled to said third lead of said first transistor.

Claim 6

The circuit of claim 4, wherein said switch comprises a second transistor.

Claim 7

The circuit of claim 1, wherein said first stage further comprises a latch circuit coupled to said output lead of said first stage.

Claim 8

The circuit of claim 1, wherein, during said second phase, when said first stage provides said second phase output signal of said first stage having a logic level different from said predetermined logic level, said first stage is configured to maintain said logic level of said second phase output signal throughout said second phase.

Claim 9

The circuit of claim 1, wherein said first stage further comprises a third transistor having a first lead coupled to a second voltage source, a second lead coupled to said clock input lead of said first stage, and a third lead coupled to said output lead of said first stage.

Claim 10

The circuit of claim 1, wherein said second stage comprises: a fourth transistor having a first lead coupled to said output lead of said first stage and having a second lead coupled to said output lead of said second stage; a fifth transistor having a first lead coupled to said second input lead of said second stage, and having a second lead coupled to said output lead of said second stage; and a sixth transistor having a first lead coupled to said output lead of said first stage and having a second lead coupled to a third lead of said fifth transistor.

Claim 11

The circuit of claim 9, wherein during said second phase: said fifth transistor is configured to be conductive, and said fourth and sixth transistors are configured so that said fourth transistor is conductive when said sixth transistor is non-conductive and said fourth transistor is non-conductive when said sixth transistor is conductive, said sixth transistor being conductive when said output signal from said first stage is at said predetermined logic level.

Claim 12

The circuit of claim 10, further comprising a second latch circuit coupling said second lead of said fourth transistor and said second lead of said fifth transistor to said output lead of said second stage.

Claim 13

The circuit of claim 1, wherein said clock signal is an only clock signal coupled to said circuit.

Claim 14

The circuit of claim 1, wherein said circuit is configured to provide said output signal of said second stage with a logic low level with a maximum delay, measured from a starting edge of said clock signal, equivalent to a sum of three gate delays.

Claim 15

The circuit of claim 1, wherein said circuit is configured to provide said output signal of said second stage with a logic high level with a maximum delay, measured from a starting edge of said clock signal, equivalent to a sum of two gate delays.

Claim 16

The circuit of claim 2 wherein said logic block comprises a plurality of n-channel transistors, wherein each transistor of said plurality of n-channel transistors has a gate coupled to a corresponding lead of said plurality of leads of said logic block.

Claim 19

The method of claim 16 wherein said function comprises a logical NAND of said plurality of data signals.

Claim 20

The method of claim 16 wherein said function comprises a logical NOR of said plurality of data signals.

Claim 21

The method of claim 16 wherein said function comprises a multiplexing operation of said plurality of data signals.

Claim 22

A flip-flop configured to operate in a first phase and a second phase, said flip-flop comprising: an input stage having: a data port wherein said data port is coupled to receive a plurality of data signals; a clock input lead wherein said clock input lead is coupled to receive a clock signal, said first phase occurring when said clock signal has a first logic level and said second phase occurring when said clock signal has a second logic level; an output lead; a logic block having a second lead coupled to said output lead of said first stage, a plurality of leads coupled to said data port, and a first lead, wherein said logic block provides a conductive path between said first and second leads of said logic block as a function of a logic state of said plurality of data signals; and a shut-off logic circuit coupling said output lead of said first stage to said second lead of said logic block, wherein: during said first phase, said input stage is operative to provide at said output lead of said input stage a first phase output signal having a predetermined logic level, and during said second phase, said input stage is operative to provide at said output lead of said input stage a second phase output signal as a function of a logic state of said plurality of data signals received at said data port of said input stage; and an output stage having a first input lead coupled to said output lead of said input stage, a second input lead coupled to said clock input lead of said input stage, and an output lead, wherein: during said first phase, said output stage is operative to maintain at said output lead of said output stage an output signal generated by said output stage prior to said first phase, said output stage maintaining said output signal of said output stage independently of said first phase output signal provided by said input stage during said first phase, and during said second phase, said output stage is operative to provide at said output lead of said output stage an output signal as a function of a logic level of said second phase output signal of said input stage and further wherein said shut-off logic circuit maintains said predetermined logic level at said output lead of said input stage throughout said second phase in response to said second phase output signal of said input stage having a logic level equivalent to said predetermined logic level throughout a shut-off delay, said shut-off delay having a predetermined time period starting when said second phase starts.

Claim 23

A flip-flop configured to operate in a first phase and a second phase, said flip-flop comprising: an input stage having: a data port wherein said data port is coupled to receive a plurality of data signals; a clock input lead wherein said clock input lead is coupled to receive a clock signal, said first phase occurring when said clock signal has a first logic level and said second phase occurring when said clock signal has a second logic level; an output lead; a logic block having a second lead coupled to said output lead of said first stage, a plurality of leads coupled to said data port, and a first lead, wherein said logic block provides a conductive path between said first and second leads of said logic block as a function of a logic state of said plurality of data signals; and a shut-off logic circuit coupling said output lead of said first stage to said second lead of said logic block, wherein: during said first phase, said input stage is operative to provide at said output lead of said input stage a first phase output signal having a predetermined logic level, and during said second phase, said input stage is operative to provide at said output lead of said input stage a second phase output signal as a function of a logic state of said plurality of data signals received at said data port of said input stage; and an output stage having a first input lead coupled to said output lead of said input stage, a second input lead coupled to said clock input lead of said input stage, and an output lead, wherein: during said first phase, said output stage is operative to maintain at said output lead of said output stage an output signal generated by said output stage prior to said first phase, said output stage maintaining said output signal of said output stage independently of said first phase output signal provided by said input stage during said first phase, and during said second phase, said output stage is operative to provide at said output lead of said output stage an output signal as a function of a logic level of said second phase output signal of said input stage and further wherein said shut-off logic circuit maintains said predetermined logic level at said output lead of said input stage throughout said second phase in response to said second phase output signal of said input stage having a logic level equivalent to said predetermined logic level throughout a shut-off delay, said shut-off delay having a predetermined time period starting when said second phase starts.

Claim 24

The flip-flop of claim 20 wherein said input stage further comprises: a switch having a first terminal coupled to a first voltage source, a second terminal coupled to said clock input lead of said first stage, and a third terminal coupled to said first lead of said login bloc, wherein said switch is configured to provide a conductive path between said first terminal and said third terminal during said second phase.

Claim 25

The flip-flop of claim 20, wherein, during said second phase, said shut-off logic circuit provides a conductive path between said output lead of said input stage and second lead of said logic block when said second phase output signal of said input stage has a logic level different from said predetermined logic level and to open-circuit said conductive path when said second phase output signal of said input stage has a logic level equivalent to said predetermined logic level for said predetermined time period.

Claim 26

The flip-flop of claim 20, wherein said clock signal is an only clock signal coupled to said flip-flop.

Claim 27

The flip-flop of claim 20, wherein said flip-flop is configured to provide said output signal of said output stage with a logic high level with a maximum delay, measured from a starting edge of said clock signal, equivalent to a sum of two gate delays.

Claim 28

The flip-flop of claim 20, wherein said flip-flop is configured to provide said output signal of said output stage with a logic low level with a maximum delay, measured from a starting edge of said clock signal, equivalent to a sum of three gate delays.

Claim 29

A computer system comprising: a memory; an interface; a peripheral coupled to said interface; and a processor coupled to said memory and said interface, said processor configured to access said memory and said interface, said processor configured to access said memory and to interact with said peripheral through said interface, said processor including a flip-flop comprising: an input stage having: a data port wherein said data port is coupled to receive a plurality of data signals; a clock input lead wherein said clock input lead is coupled to receive a clock signal; said flip-flop operates in a first phase when said clock signal has a first logic level and in a second phase when said clock signal has a second logic level; an output lead; a logic block having a second lead coupled to said output lead of said first stage, a plurality of leads coupled to said data port, and a first lead, wherein said logic block provides a conductive path between said first and second leads of said logic block as a function of a logic state of said plurality of data signals; and a shut-off logic circuit coupling said output lead of said first stage to said second lead of said logic block, wherein: during said first phase, said input stage is operative to provide at said output lead of said input stage a first phase output signal having a predetermined logic level, and during said second phase, said input stage is operative to provide at said output lead of said input stage a second phase output signal as a function of a logic state of said plurality of data signals received at said data port of said input stage; and an output stage having a first input lead coupled to said output lead of said input stage, a second input lead coupled to said clock input lead of said input stage, and an output lead, wherein: during said first phase, said output stage is operative to maintain at said output lead of said output stage an output signal generated by said output stage prior to said first phase, said output stage maintaining said output signal of said output stage independently of said first phase output signal provided by said input stage during said first phase, and during said second phase, said output stage is operative to provide at said output lead of said output stage an output signal as a function of a logic level of said second phase output signal of said input stage and further wherein said shut-off logic circuit maintains said predetermined logic level at said output lead of said input stage throughout said second phase in response to said second phase output signal of said input stage having a logic level equivalent to said predetermined logic level throughout a shut-off delay, said shut-off delay having a predetermined time period starting when said second phase starts.

Claim 30

A computer system comprising: a memory; an interface; a peripheral coupled to said interface; and a processor coupled to said memory and said interface, said processor configured to access said memory and said interface, said processor configured to access said memory and to interact with said peripheral through said interface, said processor including a flip-flop comprising: an input stage having: a data port wherein said data port is coupled to receive a plurality of data signals; a clock input lead wherein said clock input lead is coupled to receive a clock signal; said flip-flop operates in a first phase when said clock signal has a first logic level and in a second phase when said clock signal has a second logic level; an output lead; a logic block having a second lead coupled to said output lead of said first stage, a plurality of leads coupled to said data port, and a first lead, wherein said logic block provides a conductive path between said first and second leads of said logic block as a function of a logic state of said plurality of data signals; and a shut-off logic circuit coupling said output lead of said first stage to said second lead of said logic block, wherein: during said first phase, said input stage is operative to provide at said output lead of said input stage a first phase output signal having a predetermined logic level, and during said second phase, said input stage is operative to provide at said output lead of said input stage a second phase output signal as a function of a logic state of said plurality of data signals received at said data port of said input stage; and an output stage having a first input lead coupled to said output lead of said input stage, a second input lead coupled to said clock input lead of said input stage, and an output lead, wherein: during said first phase, said output stage is operative to maintain at said output lead of said output stage an output signal generated by said output stage prior to said first phase, said output stage maintaining said output signal of said output stage independently of said first phase output signal provided by said input stage during said first phase, and during said second phase, said output stage is operative to provide at said output lead of said output stage an output signal as a function of a logic level of said second phase output signal of said input stage and further wherein said shut-off logic circuit maintains said predetermined logic level at said output lead of said input stage throughout said second phase in response to said second phase output signal of said input stage having a logic level equivalent to said predetermined logic level throughout a shut-off delay, said shut-off delay having a predetermined time period starting when said second phase starts.

Claim 31

The computer system of claim 26 wherein said input stage further comprises: a switch having a first terminal coupled to a first voltage source, a second terminal coupled to said clock input lead of said first stage, and a third terminal, wherein said switch said is configured to provide a conductive path between said first terminal and said third terminal during said second phase.