Multiple compound domino logic circuit

Claim 2

A compound domino logic circuit for providing a plurality of logic outputs based on a plurality of logic inputs, comprising: a plurality of electrically isolated input logic sections, each of said input logic sections for receiving at least one logic input, and each of said input logic sections including a preliminary node defining an output of the respective section; a plurality of clocked precharge devices, each of said clocked precharge devices connected to one of said preliminary nodes for precharging said preliminary nodes to a first voltage; one or more clocked discharge devices connected to said plurality of electrically isolated input logic sections for referencing each of said input logic sections to a second voltage level; a first output logic device connected directly to at least one of said preliminary nodes including a first preliminary node for providing a first logic output; and a second output logic device connected directly to two or more of said preliminary nodes for providing a second logic output wherein one of said two or more preliminary nodes is said first preliminary node.

Claim 3

The compound domino logic circuit of claim 1 wherein said first output logic device comprises a NOR gate.

Claim 4

The compound domino logic circuit of claim 2 wherein said second output logic device comprises an inverter.

Claim 5

The compound domino logic circuit of claim 1 wherein said first output logic device comprises a NAND gate.

Claim 6

The compound domino logic circuit of claim 1 wherein one of said electrically isolated input logic sections includes an intermediate node defining a second output of said one section, connected to one of said output logic devices.

Claim 7

The compound domino logic circuit of claim 1 wherein said precharge device comprises a PMOS transistor.

Claim 8

The compound domino logic circuit of claim 1 wherein said discharge device comprises an NMOS transistor.

Claim 9

The compound domino logic circuit of claim 1 wherein said logic sections each comprise one or more NMOS transistors having a drain region connected in series with a discharge device.

Claim 10

The compound domino logic circuit of claim 8 wherein at least one of said logic section comprises one or more NMOS transistors connected in parallel to one or more of said NMOS transistors connected in series.

Claim 11

A compound domino logic circuit for providing a plurality of logic outputs, comprising: a first section comprising at least one transistor to provide a current path from a first preliminary dynamic output node to a first discharge node, and said transistor including an input to said compound domino logic circuit; a second input section comprising at least one transistor to provide a current path from a second preliminary dynamic output node to a second discharge node, said second preliminary dynamic output node being electrically independent of said first preliminary dynamic output node; at least a pair of clocked precharge transistors, each of said precharge transistors connected between a supply voltage and one of said first and second preliminary dynamic output nodes; one or more clocked discharge transistors connected to said discharge nodes; a first logic gate having inputs connected directly to said first and second preliminary dynamic output nodes, and an output comprising a first output of said compound logic circuit; and a second logic gate having at least one input connected directly to at least one of said first and second preliminary dynamic output nodes, and an output comprising a second output of said compound logic circuit.

Claim 12

A compound domino logic circuit for providing a plurality of logic outputs, comprising: a first section comprising at least one transistor to provide a current path from a first preliminary dynamic output node to a first discharge node, and said transistor including an input to said compound domino logic circuit; a second input section comprising at least one transistor to provide a current path from a second preliminary dynamic output node to a second discharge node, said second preliminary dynamic output node being electrically independent of said first preliminary dynamic output node; at least a pair of clocked precharge transistors, each of said precharge transistors connected between a supply voltage and one of said first and second preliminary dynamic output nodes; one or more clocked discharge transistors connected to said discharge nodes; a first logic gate having inputs connected directly to said first and second preliminary dynamic output nodes, and an output comprising a first output of said compound logic circuit; and a second logic gate having at least one input connected directly to at least one of said first and second preliminary dynamic output nodes, and an output comprising a second output of said compound logic circuit.

Claim 13

The compound domino logic circuit of claim 10 and further comprising a third input section comprising at least one transistor to provide a current path from a third preliminary output dynamic node to a third discharge node, said third preliminary dynamic node being electrically independent of said first and second preliminary dynamic output nodes.

Claim 14

The compound domino logic circuit of claim 11 wherein said first logic gate is further connected to said third preliminary node.

Claim 15

The compound domino logic circuit of claim 11 wherein said second logic gate is further connected to said third preliminary node.

Claim 16

The compound domino logic circuit of claim 10 wherein said transistors comprising the first and second input sections comprise NMOS transistors.

Claim 17

The compound domino logic circuit of claim 10 wherein said precharge transistors comprise PMOS transistors.

Claim 18

The compound domino logic circuit of claim 10 wherein said discharge transistors comprise NMOS transistors.

Claim 21

The method of claim 17 wherein said step of generating a first logic output comprises the step of performing a logical NOR operation on the voltages present at said first set of nodes.

Claim 22

The method of claim 17 wherein said step of generating a second logic output comprises the step of performing a logic inversion operation on the voltages present at said second set of nodes.

Claim 23

An integrated circuit including: a compound domino logic circuit for providing a plurality of logical outputs based on a plurality of logical inputs, comprising: a plurality of electrically isolated input logic sections, each said second for receiving at least one logical input, and each said section including a preliminary node defining an output of the respective section; a plurality of clocked precharged devices, each of said precharge devices connected to one of said preliminary nodes for precharging said nodes to a first voltage; one or more clocked discharge devices connected to said plurality of input logic sections referencing each said section to a second voltage level; a first output logic device connected directly to at least one of said preliminary nodes including a first preliminary node for providing a second logic output; and a second output logic device connected directly to two or more of said preliminary nodes for providing a second logical output wherein one of said two or more preliminary nodes for providing a second logical output is said first preliminary node.

Claim 24

An integrated circuit including: a compound domino logic circuit for providing a plurality of logical outputs based on a plurality of logical inputs, comprising: a plurality of electrically isolated input logic sections, each said second for receiving at least one logical input, and each said section including a preliminary node defining an output of the respective section; a plurality of clocked precharged devices, each of said precharge devices connected to one of said preliminary nodes for precharging said nodes to a first voltage; one or more clocked discharge devices connected to said plurality of input logic sections referencing each said section to a second voltage level; a first output logic device connected directly to at least one of said preliminary nodes including a first preliminary node for providing a second logic output; and a second output logic device connected directly to two or more of said preliminary nodes for providing a second logical output wherein one of said two or more preliminary nodes for providing a second logical output is said first preliminary node.

Claim 25

The integrated circuit of claim 20 wherein said first output logic device comprises a NOR gate.

Claim 26

The integrated circuit of claim 21 wherein said second output logic device comprises an inverter.

Claim 27

The integrated circuit of claim 20 wherein said first output logic device comprises a NAND gate.

Claim 28

A compound domino logic circuit for providing a plurality of logic outputs based on a plurality of logic inputs comprising: an input logic section for receiving a plurality of inputs, said logic section including a plurality of nodes defining preliminary logic outputs; a plurality of clocked precharge devices, each of said clocked precharge devices connected to one of said nodes for precharging said nodes to a first voltage; a clocked discharge device for referencing said logic section to a second voltage level; a first output logic device connected directly to at least one of said nodes including a first node to provide a first logic output; and a second output logic device connected directly to two or more of said nodes for providing a second logic output wherein one of said two or more nodes for providing a second logic output is said first node.

Claim 29

A compound domino logic circuit for providing a plurality of logic outputs based on a plurality of logic inputs comprising: an input logic section for receiving a plurality of inputs, said logic section including a plurality of nodes defining preliminary logic outputs; a plurality of clocked precharge devices, each of said clocked precharge devices connected to one of said nodes for precharging said nodes to a first voltage; a clocked discharge device for referencing said logic section to a second voltage level; a first output logic device connected directly to at least one of said nodes including a first node to provide a first logic output; and a second output logic device connected directly to two or more of said nodes for providing a second logic output wherein one of said two or more nodes for providing a second logic output is said first node.

Claim 30

The compound domino logic circuit of claim 24 wherein said second output logic device comprises a NAND gate.

Claim 31

The compound domino logic circuit of claim 24 wherein said second output logic device comprises a NOR gate.

Claim 32

The compound domino logic circuit of claim 24 wherein said first output logic device comprises an inverter.