Transistor having an improved salicided gate and method of construction

Claim 1

A method of forming an amorphous region in a gate of a transistor, the method comprising: forming the gate separated from a substrate by a gate insulator; forming a spacer outwardly from the gate, the spacer exposing a top region and a side region of the gate; and irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle to form a post amorphous region, the angle formed between the ion beam and an axis normal to a surface of the substrate and in the range of 5° to 80°.

Claim 2

A method of forming an amorphous region in a gate of a transistor, the method comprising: forming the gate separated from a substrate by a gate insulator; forming a spacer outwardly from the gate, the spacer exposing a top region and a side region of the gate; and irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle to form a post amorphous region, the angle formed between the ion beam and an axis normal to a surface of the substrate and in the range of 5° to 80°.

Claim 12

A method of forming a semiconductor component with a transistor having a salicided gate, the method of forming the salicided gate comprising the steps of: forming a gate separated from a substrate by a gate insulator; forming a buffer layer outwardly from the substrate and the gate; forming a spacer layer outwardly from the buffer layer; anisotropically etching the spacer layer to form a spacer, the spacer exposing a post region of the gate and a gap region of the substrate; irradiating the post region and the gap region using an ion beam directed at the gate at an angle to form a post amorphous region and a gap amorphous region, respectively; wherein the angle is formed between the ion beam and an axis normal to a surface of the substrate and operates to reduce ion implantation damage to the substrate, the angle in the range of 5° to 80°; forming a reactive layer adjacent the post amorphous region and the gap amorphous region; forming a salicidation region between the post amorphous region and the reactive layer by thermally treating the reactive layer, the salicidation region of the gate forming, at least in part, the salicided gate of the transistor; and removing the unreacted portion of reactive layer.

Claim 13

A method of forming a semiconductor component with a transistor having a salicided gate, the method of forming the salicided gate comprising the steps of: forming a gate separated from a substrate by a gate insulator; forming a buffer layer outwardly from the substrate and the gate; forming a spacer layer outwardly from the buffer layer; anisotropically etching the spacer layer to form a spacer, the spacer exposing a post region of the gate and a gap region of the substrate; irradiating the post region and the gap region using an ion beam directed at the gate at an angle to form a post amorphous region and a gap amorphous region, respectively; wherein the angle is formed between the ion beam and an axis normal to a surface of the substrate and operates to reduce ion implantation damage to the substrate, the angle in the range of 5° to 80°; forming a reactive layer adjacent the post amorphous region and the gap amorphous region; forming a salicidation region between the post amorphous region and the reactive layer by thermally treating the reactive layer, the salicidation region of the gate forming, at least in part, the salicided gate of the transistor; and removing the unreacted portion of reactive layer.

Claim 18

A method of forming a salicidation region in a gate of a transistor, the method comprising: forming the gate separated from a substrate by a gate insulator; forming a buffer layer outwardly from the substrate and the gate; forming a spacer layer outwardly from the buffer layer; etching the spacer layer anisotropically to form a spacer, the spacer exposing a top region and a side region of the gate; forming a post amorphous region in the gate by irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle, the angle formed between the ion beam and an axis normal to a surface of the substrate, the angle in the range of 5° to 80°; removing the exposed portions of the buffer layer; forming a reactive layer adjacent the post amorphous region; heating the reactive layer to form a salicidation region between the post amorphous region and the reactive layer; and removing the unreacted portion of the reactive layer.

Claim 19

A method of forming a salicidation region in a gate of a transistor, the method comprising: forming the gate separated from a substrate by a gate insulator; forming a buffer layer outwardly from the substrate and the gate; forming a spacer layer outwardly from the buffer layer; etching the spacer layer anisotropically to form a spacer, the spacer exposing a top region and a side region of the gate; forming a post amorphous region in the gate by irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle, the angle formed between the ion beam and an axis normal to a surface of the substrate, the angle in the range of 5° to 80°; removing the exposed portions of the buffer layer; forming a reactive layer adjacent the post amorphous region; heating the reactive layer to form a salicidation region between the post amorphous region and the reactive layer; and removing the unreacted portion of the reactive layer.