← Back to Patent Explorer
US5879975A Expired / Lapsed US ⏱️ 0.0 years remaining

Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

Assignee: Advanced Micro Devices Inc
•
Filing: 1997-09-05
•
Granted: 1999-03-09
•
Expires: 2017-09-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen implantation at high dosages to prevent subsequent impurity penetration through the gate dielectric layer, e.g., B penetration, amorphizes the upper portion of the gate electrode layer resulting in concave side surfaces upon etching to form the gate electrode. Heat treatment performed after nitrogen implantation can restore sufficient crystallinity so that, after etching the gate electrode layer, the side surfaces of the resulting gate electrode are substantially parallel.

Inventors

  • 👤 Olov Karlsson
  • 👤 Effiong Ibok
  • 👤 Dong-Hyuk Ju
  • 👤 Scott A. Bell
  • 👤 Daniel A. Steckert
  • 👤 Robert Ogle

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 18:40
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 99 words
A method of manufacturing a semiconductor device, which method comprises: forming a polycrystalline silicon layer on an upper surface of a semiconductor substrate with a dielectric layer therebetween; implanting nitrogen atoms into the polycrystalline silicon layer at a dosage sufficient to amorphize an upper portion of the polycrystalline silicon layer; heat treating said nitrogen implanted polycrystalline silicon layer under conditions sufficient to restore crystallinity to the amorphized upper portion of the polycrystalline silicon layer; and etching the heat treated nitrogen implanted layer to form a gate electrode, wherein said heat treating improves the etch profile of the gate electrode.
Claim 2
Independent Claim 99 words
A method of manufacturing a semiconductor device, which method comprises: forming a polycrystalline silicon layer on an upper surface of a semiconductor substrate with a dielectric layer therebetween; implanting nitrogen atoms into the polycrystalline silicon layer at a dosage sufficient to amorphize an upper portion of the polycrystalline silicon layer; heat treating said nitrogen implanted polycrystalline silicon layer under conditions sufficient to restore crystallinity to the amorphized upper portion of the polycrystalline silicon layer; and etching the heat treated nitrogen implanted layer to form a gate electrode, wherein said heat treating improves the etch profile of the gate electrode.
Claim 3
Dependent Claim 38 words
The method according to claim 1, comprising implanting nitrogen at a dosage sufficient to amorphize the upper portion extending up to about 50% of the polycrystalline silicon gate electrode layer toward the upper surface of the semiconductor substrate.
Claim 4
Dependent Claim 22 words
The method according to claim 1, comprising: etching the polycrystalline silicon layer to form a gate electrode having substantially parallel side surfaces.
Claim 5
Dependent Claim 30 words
The method according to claim 3, comprising etching the polycrystalline silicon layer to form a gate electrode having side surfaces substantially perpendicular to the upper surface of the semiconductor substrate.
Claim 6
Dependent Claim 26 words
The method according to claim 3, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 600° C. to about 1,000° C.
Claim 7
Dependent Claim 37 words
The method according to claim 5, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 850° C. for about 30 seconds in an atmosphere comprising nitrogen and about 10 volume percent oxygen.
Claim 8
Dependent Claim 30 words
The method according to claim 5, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 750° C. for about 30 minutes in a nitrogen atmosphere.
Claim 9
Dependent Claim 35 words
The method according to claim 1, further comprising: forming a mask on the nitrogen implanted polycrystalline silicon layer after heat treating; and etching the heat treated masked polycrystalline silicon layer to form the gate electrode.
Claim 10
Dependent Claim 14 words
The method according to claim 1, wherein the semiconductor substrate comprises an N-type impurity.
Claim 11
Dependent Claim 29 words
The method according to claim 9, further comprising forming P-impurity type source/drain regions in the semiconductor substrate on opposite sides of the gate electrode to form a P-channel MOS.
Claim 12
Dependent Claim 67 words
The method according to claim 1, comprising: implanting nitrogen under conditions sufficient to amorphize an upper portion of the polycrystalline silicon layer; heat treating to restore sufficient crystallinity to the amorphized upper portion to enable formation of a gate electrode having substantially parallel side surfaces upon etching the polycrystalline silicon film; and etching the polycrystalline silicon film to form a gate electrode having substantially parallel side surfaces.
Claim 13
Dependent Claim 32 words
The method according to claim 11, comprising etching the heat treated polycrystalline silicon film to form a gate electrode having side surfaces substantially perpendicular to the upper surface of the semiconductor substrate.
Claim 14
Dependent Claim 18 words
The method according to claim 1, wherein the dielectric layer has a thickness less than about 60 Å.
Claim 15
Dependent Claim 20 words
The method according to claim 1, comprising heat treating the nitrogen implanted polycrystalline silicon layer before depositing any layer thereon.

References Cited (Backward Citations)

US4351695A Cited
US4358326A Cited
US4682407A Cited
US4897368A Cited
US4900396A Cited
US4818711A Cited
US4925805A Cited
US4914046A Cited
US5464792A Cited
US5508212A Cited
US5605848A Cited
US5633200A Cited
US5739064A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-08 2002-09-07 2003-03-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-08 2006-09-07 2007-03-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-03-08 2010-09-07 2011-03-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag