Patent US6037640A successfully refreshed from Google Patents.
US6037640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ultra-shallow semiconductor junction formation
Assignee: International Business Machines Corp
•
Filing: 1998-05-12
•
Granted: 2000-03-14
•
Expires: 2018-05-12
Abstract
Abstract A method for fabricating an ultra-shallow semi-conductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.
Inventors
- 👤 Kam Leung Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:14
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10P; H10P30/00; H10P30/20; H10P30/21; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D62/40; H10D84/02; H10D84/03; H10D84/038; H10P30/202; H10P30/204; H10P30/208; H10P30/225; H10P30/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
108 words
A structure having an abrupt p-n junction, said structure comprising a shallow implant region defined by dopant material of a first conductivity type formed in a surface of a semiconductor substrate of a second conductivity type, said substrate comprising a region of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth, said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary.
Claim 2
Dependent Claim
108 words
A structure having an abrupt p-n junction, said structure comprising a shallow implant region defined by dopant material of a first conductivity type formed in a surface of a semiconductor substrate of a second conductivity type, said substrate comprising a region of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth, said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary.
Claim 3
Dependent Claim
15 words
The structure of in claim 1, wherein said second depth is less than 500 Å.
Claim 4
Dependent Claim
30 words
The structure of claim 1, wherein the change of concentration of said dopant material at the boundary junction is measured at a dopant concentration of 1×10 18 /cm 2 .
Claim 5
Dependent Claim
13 words
The structure of claim 1, wherein said first depth is about 10,000 Å.
Claim 6
Dependent Claim
142 words
A field effect transistor comprising a microelectronic device comprising a source region and a drain region formed in mutually spaced adjacency in a surface of a semiconductor substrate, a pair of said shallow implant regions being disposed between and formed as spaced-apart extensions of said source and drain regions to form a channel region between the spaced-apart shallow implant regions, and a gate electrode overlying said channel region, wherein said semiconductor substrate contains regions of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth and said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary.
Claim 7
Dependent Claim
142 words
A field effect transistor comprising a microelectronic device comprising a source region and a drain region formed in mutually spaced adjacency in a surface of a semiconductor substrate, a pair of said shallow implant regions being disposed between and formed as spaced-apart extensions of said source and drain regions to form a channel region between the spaced-apart shallow implant regions, and a gate electrode overlying said channel region, wherein said semiconductor substrate contains regions of coalesced high concentrations of interstitial ions of said semiconductor substrate disposed substantially at a first depth and said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant material at a boundary junction of said shallow implant region changes by a factor of 10 within a distance of less than 60 Å measured at, and perpendicular to, said boundary.
Claim 8
Dependent Claim
22 words
The field effect transistor of claim 5, wherein the distance between said spaced-apart shallow implant regions is less than about 2500 Å.
Claim 9
Dependent Claim
16 words
The field effect transistor of claim 5, wherein said second depth is less than 500 Å.
Claim 10
Dependent Claim
32 words
The field effect transistor of claim 5, wherein the change of concentration of said dopant material at the boundary junction is measured at a dopant concentration of 1×10 18 /cm 2 .
Claim 11
Dependent Claim
15 words
The field effect transistor of claim 5, wherein said first depth is about 10,000 Å.
References Cited (Backward Citations)
US5384279A
Cited
US5254484A
Cited
US5512470A
Cited
US5355011A
Cited
US5897363A
Cited
US5895954A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |