Patent US6031411A successfully refreshed from Google Patents.
US6031411A
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Low power substrate bias circuit
Assignee: Texas Instruments Inc
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Filing: 1994-08-09
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Granted: 2000-02-29
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Expires: 2014-08-09
Abstract
Abstract A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.
Inventors
- 👤 Ching-Yuh Tsay
- 👤 Hugh P. McAdams
- 👤 WahKit Loh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:03
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/50
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
139 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a control circuit, responsive to a plurality of input signals, for activating only one of N enable signals at any time, wherein N is greater than one; a plurality of N bias circuits, each having an output terminal and an enable terminal, the enable terminal receiving one of the enable signals to enable only one of the bias circuits at any time for transferring charge between the output terminal and a first reference supply, thereby generating the bias at the output terminal; a common bias terminal connected to the output terminal of each of the bias circuits; and a detector circuit, responsive to the bias of the common bias terminal, for providing one input signal to the control circuit for enabling one of the bias circuits.
Claim 2
Dependent Claim
139 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a control circuit, responsive to a plurality of input signals, for activating only one of N enable signals at any time, wherein N is greater than one; a plurality of N bias circuits, each having an output terminal and an enable terminal, the enable terminal receiving one of the enable signals to enable only one of the bias circuits at any time for transferring charge between the output terminal and a first reference supply, thereby generating the bias at the output terminal; a common bias terminal connected to the output terminal of each of the bias circuits; and a detector circuit, responsive to the bias of the common bias terminal, for providing one input signal to the control circuit for enabling one of the bias circuits.
Claim 3
Dependent Claim
32 words
The circuit of claim 1 wherein at least one of the bias circuits comprises an oscillator circuit and a pump circuit, the oscillator circuit being responsive to one of the enable signals.
Claim 4
Dependent Claim
18 words
The circuit of claim 2 wherein the common bias terminal is a substrate terminal of the semiconductor device.
Claim 5
Dependent Claim
20 words
The circuit of claim 2 wherein the common bias terminal is a second reference supply terminal of the semiconductor device.
Claim 6
Independent Claim
111 words
A method of generating a bias for a semiconductor device, including the steps of: activating only one of N enable signals at any time in response to a plurality of input signals, wherein N is greater than one; enabling only one of N bias circuits at any time in response to the one of N enable signals for transferring charge between a common bias terminal and a first reference supply wherein a detector circuit, responsive to the potential of the common bias terminal, provides one input signal to a control circuit for enabling one of the bias circuits; and generating the bias at the common bias terminal by the transferring charge.
Claim 7
Independent Claim
111 words
A method of generating a bias for a semiconductor device, including the steps of: activating only one of N enable signals at any time in response to a plurality of input signals, wherein N is greater than one; enabling only one of N bias circuits at any time in response to the one of N enable signals for transferring charge between a common bias terminal and a first reference supply wherein a detector circuit, responsive to the potential of the common bias terminal, provides one input signal to a control circuit for enabling one of the bias circuits; and generating the bias at the common bias terminal by the transferring charge.
Claim 8
Dependent Claim
32 words
The method of claim 5 wherein at least one of the bias circuits comprises an oscillator circuit and a pump circuit, the oscillator circuit being responsive to one of the enable signals.
Claim 9
Dependent Claim
18 words
The method of claim 6 wherein the common bias terminal is a substrate terminal of the semiconductor device.
Claim 10
Dependent Claim
20 words
The method of claim 6 wherein the common bias terminal is a second reference supply terminal of the semconductor device.
Claim 11
Dependent Claim
140 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a control circuit, responsive to a plurality of input signals, for activating only one of N enable signals at any time, wherein N is greater than one; a plurality of N bias circuits, each having an output terminal and an enable terminal, the enable terminal receiving one of the enable signals to enable only one of the bias circuits at any time for transferring charge between the output terminal and a first reference supply, thereby generating the bias at the output terminal; and a common bias terminal connected to the output terminal of each of the bias circuits wherein the common bias terminal is a second reference supply terminal of the semiconductor device and wherein the bias at the second reference supply terminal is a high voltage.
Claim 12
Dependent Claim
140 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a control circuit, responsive to a plurality of input signals, for activating only one of N enable signals at any time, wherein N is greater than one; a plurality of N bias circuits, each having an output terminal and an enable terminal, the enable terminal receiving one of the enable signals to enable only one of the bias circuits at any time for transferring charge between the output terminal and a first reference supply, thereby generating the bias at the output terminal; and a common bias terminal connected to the output terminal of each of the bias circuits wherein the common bias terminal is a second reference supply terminal of the semiconductor device and wherein the bias at the second reference supply terminal is a high voltage.
Claim 13
Independent Claim
112 words
A method of generating a bias for a semiconductor device, including the steps of: activating only one of N enable signals at any time in response to a plurality of input signals, wherein N is greater than one; enabling only one of N bias circuits at any time in response to the one of N enable signals for transferring charge between a common bias terminal and a first reference supply; and generating the bias at the common bias terminal by the transferring charge wherein the common bias terminal is a second reference supply terminal of the semiconductor device and wherein the bias at the second reference supply terminal is a high voltage.
Claim 14
Independent Claim
112 words
A method of generating a bias for a semiconductor device, including the steps of: activating only one of N enable signals at any time in response to a plurality of input signals, wherein N is greater than one; enabling only one of N bias circuits at any time in response to the one of N enable signals for transferring charge between a common bias terminal and a first reference supply; and generating the bias at the common bias terminal by the transferring charge wherein the common bias terminal is a second reference supply terminal of the semiconductor device and wherein the bias at the second reference supply terminal is a high voltage.
Claim 15
Dependent Claim
144 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a common bias terminal; a plurality of bias circuits, each having an output terminal coupled to the common bias terminal and having an input terminal; a detector circuit, responsive to the bias at the common bias terminal, for producing a first output signal; and a control circuit having a plurality of output terminals, each output terminal being coupled to one input terminal of at least one bias circuit for enabling the at least one bias circuit, and having a first input terminal for receiving the first output signal, a second input terminal for receiving a first input signal corresponding to a first mode of operation of the semiconductor device and a third input terminal for receiving a second input signal corresponding to a second mode of operation of the semiconductor device.
Claim 16
Dependent Claim
144 words
A circuit for generating a bias for a semiconductor device, the circuit comprising: a common bias terminal; a plurality of bias circuits, each having an output terminal coupled to the common bias terminal and having an input terminal; a detector circuit, responsive to the bias at the common bias terminal, for producing a first output signal; and a control circuit having a plurality of output terminals, each output terminal being coupled to one input terminal of at least one bias circuit for enabling the at least one bias circuit, and having a first input terminal for receiving the first output signal, a second input terminal for receiving a first input signal corresponding to a first mode of operation of the semiconductor device and a third input terminal for receiving a second input signal corresponding to a second mode of operation of the semiconductor device.
Claim 17
Dependent Claim
20 words
A circuit as in claim 11 wherein the first mode of operation of the semiconductor device is an active cycle.
Claim 18
Dependent Claim
20 words
A circuit as in claim 12 wherein the second mode of operation of the semiconductor device is a burn-in mode.
Claim 19
Dependent Claim
21 words
A circuit as in claim 12 wherein the second mode of operation of the semiconductor device is a high voltage mode.
Claim 20
Dependent Claim
21 words
A circuit as in claim 12 wherein the second mode of operation of the semiconductor device is a parallel test mode.
Claim 21
Dependent Claim
12 words
The circuit of claim 12 wherein the bias is a substrate voltage.
Claim 22
Dependent Claim
12 words
The circuit of claim 12 wherein the bias is a high voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-28 | 2003-08-30 | 2004-02-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-28 | 2007-08-30 | 2008-02-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-28 | 2011-08-30 | 2012-02-29 | $7700.00 | Window Closed / Lapsed |