Method of manufacturing a semiconductor device

Claim 1

A method of manufacturing a semiconductor device for forming bumps to be electrically and mechanically connected to a circuit board on a semiconductor element having pads, comprising the steps of: forming a first interlayer insulator on said semiconductor element, and opening portions, directly over said pads, of said first interlayer insulator for exposing said pads therefrom; forming wiring portions, each wiring portion having a pattern extending from one of said pads to a bump forming position on said semiconductor element which is not directly over said one of said pads, on said first interlayer insulator; forming a second intcrlaycr insulator on said first interlayer insulator in such a manner as to cover said wiring portions, and opening portions, directly over said bump forming positions, of said second interlayer insulator for exposing said wiring portions therefrom; forming a conducting layer on the surface, formed with said second interlayer insulator, of said semiconductor element; forming a plating resist layer on said conducting layer, and opening portions, directly over said bump forming positions, of said plating resist for exposing said conducting layer therefrom; and dipping the surface, formed with said plating resist layer, of said semiconductor element in an electrolytic solution, followed by current-carrying, to thereby form bumps in said opening portions directly over said bump forming positions wherein each of said bumps is directly connected to said conducting layer at a respective bump forming position.

Claim 2

A method of manufacturing a semiconductor device for forming bumps to be electrically and mechanically connected to a circuit board on a semiconductor element having pads, comprising the steps of: forming a first interlayer insulator on said semiconductor element, and opening portions, directly over said pads, of said first interlayer insulator for exposing said pads therefrom; forming wiring portions, each wiring portion having a pattern extending from one of said pads to a bump forming position on said semiconductor element which is not directly over said one of said pads, on said first interlayer insulator; forming a second intcrlaycr insulator on said first interlayer insulator in such a manner as to cover said wiring portions, and opening portions, directly over said bump forming positions, of said second interlayer insulator for exposing said wiring portions therefrom; forming a conducting layer on the surface, formed with said second interlayer insulator, of said semiconductor element; forming a plating resist layer on said conducting layer, and opening portions, directly over said bump forming positions, of said plating resist for exposing said conducting layer therefrom; and dipping the surface, formed with said plating resist layer, of said semiconductor element in an electrolytic solution, followed by current-carrying, to thereby form bumps in said opening portions directly over said bump forming positions wherein each of said bumps is directly connected to said conducting layer at a respective bump forming position.