US6028993A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timed circuit simulation in hardware using FPGAs
Assignee: Lattice Semiconductor Corp
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Filing: 1997-01-10
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Granted: 2000-02-22
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Expires: 2017-01-10
Abstract
Abstract A logic circuit is simulated for mapping and emulation on a field programmable gate array-based platform by mapping one or more of the circuit delays onto delay elements in the FPGA-based platform. The operations of the delay elements are controlled by one or more simulations clocks that are different from any user-specified clocks.
Inventors
- 👤 Meng-Lin Yu
- 👤 P. A. Subrahmanyam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
185 words
A method for simulating an original logic circuit as a hardware simulation logic circuit implemented on a field programmable gate array (FPGA)-based platform comprising the steps of: (a) simulating each element in the original logic circuit with a corresponding simulated element of the simulation logic circuit, wherein each simulated element is controlled by one or more circuit clocks; (b) implementing one or more additional physical delay elements in the simulation logic circuit in order to simulate one or more circuit timing delays of the original logic circuit wherein: the one or more additional physical delay elements do not directly correspond to physical elements in the original logic circuit; and the one or more circuit timing delays are mapped onto the one or more physical delay elements in the FPGA-based platform; (c) implementing one or more simulation clocks on the FPGA independent of and asynchronous with the one or more circuit clocks; and (d) simulating processing of the original logic circuit using the FPGA-based platform, wherein the one or more additional physical delay elements are controlled by the one or more simulation clocks on the FPGA.
Claim 2
Independent Claim
185 words
A method for simulating an original logic circuit as a hardware simulation logic circuit implemented on a field programmable gate array (FPGA)-based platform comprising the steps of: (a) simulating each element in the original logic circuit with a corresponding simulated element of the simulation logic circuit, wherein each simulated element is controlled by one or more circuit clocks; (b) implementing one or more additional physical delay elements in the simulation logic circuit in order to simulate one or more circuit timing delays of the original logic circuit wherein: the one or more additional physical delay elements do not directly correspond to physical elements in the original logic circuit; and the one or more circuit timing delays are mapped onto the one or more physical delay elements in the FPGA-based platform; (c) implementing one or more simulation clocks on the FPGA independent of and asynchronous with the one or more circuit clocks; and (d) simulating processing of the original logic circuit using the FPGA-based platform, wherein the one or more additional physical delay elements are controlled by the one or more simulation clocks on the FPGA.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the one or more simulation clocks are different from any other circuit clock.
Claim 4
Dependent Claim
41 words
The method of claim 1, wherein the platform comprises primitives and physical delay elements, one or more zero-delay logic blocks are mapped onto combinations of primitives, one or more non-zero circuit timing delays are mapped onto combinations of physical delay elements.
Claim 5
Dependent Claim
20 words
The method of claim 3, wherein the non-zero physical delay elements are driven by the one or more simulation clocks.
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein at least one part of the timing sequence of the logic circuit is preserved by mapping a non-zero physical delay element.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein at least one of the physical delay elements is a flip-flop.
Claim 8
Dependent Claim
17 words
The method of claim 1, wherein the physical delay elements are left in the simulated logic circuit.
Claim 9
Dependent Claim
16 words
The method of claim 1, wherein hold-time violations and violations other than hold-time violations are identified.
Claim 10
Dependent Claim
15 words
The method of claim 1, wherein the logic circuit being simulated is an asynchronous circuit.
Claim 11
Dependent Claim
14 words
The method of claim 1, wherein the simulated logic circuit is mapped in parallel.
Claim 12
Dependent Claim
19 words
The method of claim 1, wherein the circuit timing delays are explicitly controlled by simulating the physical delay elements.
Claim 13
Dependent Claim
125 words
The method of claim 1, wherein: the one or more simulation clocks are different from any other circuit clock; the platform comprises primitives and physical delay elements, one or more zero-delay logic blocks are mapped onto combinations of primitives, one or more non-zero circuit timing delays are mapped onto combinations of physical delay elements; at least one part of the timing sequence of the logic circuit is preserved by mapping a non-zero physical delay element; at least one of the physical delay elements is a flip-flop; the physical delay elements are left in the simulated logic circuit; hold-time violations and violations other than hold-time violations are identified; the logic circuit being simulated is an asynchronous circuit; and the simulated logic circuit is mapped in parallel.
Claim 14
Dependent Claim
124 words
An FPGA-based platform on which is programmed a hardware simulation logic circuit corresponding to an original logic circuit, wherein the simulation logic circuit implemented on the FPGA-based platform comprises: (a) a simulated element corresponding to each element in the original logic circuit, wherein each simulated element is controlled by one or more circuit clocks; (b) one or more additional physical delay elements that simulate one or more circuit timing delays of the original logic circuit, wherein the one or more additional physical delay elements do not directly correspond to any physical elements in the original logic circuit; and (c) one or more simulation clocks independent of and asynchronous with each circuit clock and configured to control the one or more additional physical delay elements.
Claim 15
Dependent Claim
124 words
An FPGA-based platform on which is programmed a hardware simulation logic circuit corresponding to an original logic circuit, wherein the simulation logic circuit implemented on the FPGA-based platform comprises: (a) a simulated element corresponding to each element in the original logic circuit, wherein each simulated element is controlled by one or more circuit clocks; (b) one or more additional physical delay elements that simulate one or more circuit timing delays of the original logic circuit, wherein the one or more additional physical delay elements do not directly correspond to any physical elements in the original logic circuit; and (c) one or more simulation clocks independent of and asynchronous with each circuit clock and configured to control the one or more additional physical delay elements.
Claim 16
Dependent Claim
20 words
The FPGA-based platform of claim 13, wherein the one or more simulation clocks are different from any other circuit clock.
Claim 17
Dependent Claim
42 words
The FPGA-based platform of claim 13, wherein the platform comprises primitives and physical delay elements, one or more zero-delay logic blocks are mapped onto combinations of primitives, one or more non-zero circuit timing delays are mapped onto combinations of physical delay elements.
Claim 18
Dependent Claim
21 words
The FPGA-based platform of claim 15, wherein the non-zero physical delay elements are driven by the one or more simulation clocks.
Claim 19
Dependent Claim
28 words
The FPGA-based platform of claim 13, wherein at least one part of the timing sequence of the logic circuit is preserved by mapping a non-zero physical delay element.
Claim 20
Dependent Claim
18 words
The FPGA-based platform of claim 13, wherein at least one of the physical delay elements is a flip-flop.
Claim 21
Dependent Claim
18 words
The FPGA-based platform of claim 13, wherein the physical delay elements are left in the simulated logic circuit.
Claim 22
Dependent Claim
17 words
The FPGA-based platform of claim 13, wherein hold-time violations and violations other than hold-time violations are identified.
Claim 23
Dependent Claim
16 words
The FPGA-based platform of claim 13, wherein the logic circuit being simulated is an asynchronous circuit.
Claim 24
Dependent Claim
15 words
The FPGA-based platform of claim 13, wherein the simulated logic circuit is mapped in parallel.
Claim 25
Dependent Claim
20 words
The FPGA-based platform of claim 13, wherein the circuit timing delays are explicitly controlled by simulating the physical delay elements.
Claim 26
Dependent Claim
126 words
The FPGA-based platform of claim 13, wherein: the one or more simulation clocks are different from any other circuit clock; the platform comprises primitives and physical delay elements, one or more zero-delay logic blocks are mapped onto combinations of primitives, one or more non-zero circuit timing delays are mapped onto combinations of physical delay elements; at least one part of the timing sequence of the logic circuit is preserved by mapping a non-zero physical delay element; at least one of the physical delay elements is a flip-flop; the physical delay elements are left in the simulated logic circuit; hold-time violations and violations other than hold-time violations are identified; the logic circuit being simulated is an asynchronous circuit; and the simulated logic circuit is mapped in parallel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |