US5677848A
Expired / Lapsed
US
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Method to derive the functionality of a digital circuit from its mask layout
Assignee: Nokia of America Corp
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Filing: 1995-11-03
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Granted: 1997-10-14
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Expires: 2015-11-03
Abstract
Abstract A method for generating a simplified model of a complex binary transistor circuit. A set of Boolean functions are derived for the circuit and these functions are tested to determine if the circuit is stable and binary. All intermediate transient circuit configurations are eliminated so that only direct transitions between stable circuit configurations remain. If the circuit is also combinational, a logic circuit is generated. If the circuit is not combinational but if there is a clock input to the circuit that controls the values of the node (the circuit exhibits synchronous behavior) and all nodes in the circuit are well-defined (either combinational or level-sensitive), a logic circuit is generated. The logic circuit is processed to generate a further simplified logic circuit by merging different types of latches and other logic elements and removing duplicative logic elements.
Inventors
- 👤 Kanwar J. Singh
- 👤 Pasupathi A. Subrahmanyam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:26
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
397 words
A method for generating a gate-level logic model of a transistor circuit having a plurality of circuit nodes, the circuit attaining an output value in response to an input condition, comprising: (A) deriving a plurality of Boolean functions for the circuit that describe operation of the circuit and provide signal values at nodes of the circuit upon application of the input condition; (B) analyzing the Boolean functions to determine whether the circuit is stable; (C) upon determining in step (B) that the circuit is stable, evaluating the Boolean functions to determine whether all possible output values have binary values; (D) upon determining in step (C) that all possible output values of the circuit have binary values, generating a binary stable simulation relation for the circuit from the Boolean functions by: (i) determining all stable signal values of the nodes of the circuit; (ii) determining all stable node signal values of the circuit that result upon a change in an input condition; and (iii) modifying the Boolean functions to eliminate all intermediate node signal values that are not stable node signal values to generate the binary stable simulation relation; (E) evaluating the binary stable simulation relation to determine whether each input condition generates only one binary circuit output value; (F) upon determining in step (E) that each input condition generates only one binary circuit output value for each input condition, generating the gate-level logic model of the circuit from the binary stable simulation relation; (G) upon determining in step (E) that each input condition generates more than one binary circuit output value, determining whether any input conditions reflect a clock signal; (H) upon determining in step (G) that at least one input condition reflects a clock signal, evaluating the binary stable simulation relation for each of the nodes of the circuit to determine whether signal values for each of the nodes are well-defined for all possible input conditions by determining for each node whether the node is one of combinational and level-sensitive; (I) upon determining in step (H) that signal values for each of the nodes are well-defined for all possible input conditions, functionally modifying the binary stable simulation relation to reflect which nodes have been determined in step (H) to be one of combinational and level-sensitive; and (J) generating the gate-level logic model of the circuit from the modified binary stable simulation relation generated in step (I).
Claim 2
Independent Claim
397 words
A method for generating a gate-level logic model of a transistor circuit having a plurality of circuit nodes, the circuit attaining an output value in response to an input condition, comprising: (A) deriving a plurality of Boolean functions for the circuit that describe operation of the circuit and provide signal values at nodes of the circuit upon application of the input condition; (B) analyzing the Boolean functions to determine whether the circuit is stable; (C) upon determining in step (B) that the circuit is stable, evaluating the Boolean functions to determine whether all possible output values have binary values; (D) upon determining in step (C) that all possible output values of the circuit have binary values, generating a binary stable simulation relation for the circuit from the Boolean functions by: (i) determining all stable signal values of the nodes of the circuit; (ii) determining all stable node signal values of the circuit that result upon a change in an input condition; and (iii) modifying the Boolean functions to eliminate all intermediate node signal values that are not stable node signal values to generate the binary stable simulation relation; (E) evaluating the binary stable simulation relation to determine whether each input condition generates only one binary circuit output value; (F) upon determining in step (E) that each input condition generates only one binary circuit output value for each input condition, generating the gate-level logic model of the circuit from the binary stable simulation relation; (G) upon determining in step (E) that each input condition generates more than one binary circuit output value, determining whether any input conditions reflect a clock signal; (H) upon determining in step (G) that at least one input condition reflects a clock signal, evaluating the binary stable simulation relation for each of the nodes of the circuit to determine whether signal values for each of the nodes are well-defined for all possible input conditions by determining for each node whether the node is one of combinational and level-sensitive; (I) upon determining in step (H) that signal values for each of the nodes are well-defined for all possible input conditions, functionally modifying the binary stable simulation relation to reflect which nodes have been determined in step (H) to be one of combinational and level-sensitive; and (J) generating the gate-level logic model of the circuit from the modified binary stable simulation relation generated in step (I).
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein the step (H) of determining whether a node is combinational comprises determining whether a function describing the node for a clock input is identical to another function describing the node for another clock input.
Claim 4
Dependent Claim
40 words
The method of claim 1, wherein the step (H) of determining whether a node is level-sensitive comprises determining whether functions describing the node change during one phase of each clock signal and not during another phase of the clock signal.
Claim 5
Dependent Claim
40 words
The method of claim 2, wherein the step (H) of determining whether a node is level-sensitive comprises determining whether functions describing the node change during one phase of each clock signal and not during another phase of the clock signal.
Claim 6
Dependent Claim
40 words
The method of claim 1, wherein the step (B) of determining whether the circuit is stable comprises determining that the circuit is stable if the node signal values remain the same as long as the input condition remains the same.
Claim 7
Dependent Claim
47 words
The method of claim 1, wherein the step (B) of determining whether the circuit is stable comprises determining that the circuit is stable if each possible input condition result in respective node signal values that remain the same as long as the input condition remains the same.
Claim 8
Dependent Claim
41 words
The method of claim 1, wherein the step (D) of determining stable node signal values comprises determining that a node signal value is stable if the node signal value remains the same as long as the input condition remains the same.
Claim 9
Dependent Claim
25 words
The method of claim 1, further comprising (K) processing the gate-level logic model so as to simplify the model by combining elements in the model.
Claim 10
Independent Claim
100 words
A method for generating a gate-level model of a transistor circuit from a plurality of Boolean functions describing the circuit, the circuit having a plurality of circuit nodes and attaining an output value in response to an input condition, comprising: determining all stable signal values of the nodes of the circuit; determining all stable node signal values of the circuit that result upon a change in an input condition; modifying the Boolean functions to eliminate all intermediate node signal values that are not stable node signal values; generating the gate-level logic model of the circuit from the modified Boolean functions.
Claim 11
Independent Claim
100 words
A method for generating a gate-level model of a transistor circuit from a plurality of Boolean functions describing the circuit, the circuit having a plurality of circuit nodes and attaining an output value in response to an input condition, comprising: determining all stable signal values of the nodes of the circuit; determining all stable node signal values of the circuit that result upon a change in an input condition; modifying the Boolean functions to eliminate all intermediate node signal values that are not stable node signal values; generating the gate-level logic model of the circuit from the modified Boolean functions.
Claim 12
Dependent Claim
40 words
The method of claim 9, wherein the steps of determining stable node signal values comprises determining that a node signal value is stable if the node signal value remains the same as long as the input condition remains the same.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |