US5721695A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Simulation by emulating level sensitive latches with edge trigger latches
Assignee: GlobalFoundries Inc
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Filing: 1994-10-17
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Granted: 1998-02-24
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Expires: 2014-10-17
Abstract
Abstract A hardware simulation system is disclosed which includes a high frequency clock which is gated with a system clock to produce a high frequency enabled clock. The high frequency enabled clock is used to clock an edge triggered latch within the hardware simulation system. Thus, the system advantageously emulates level sensitive latches using edge triggered latches.
Inventors
- 👤 Brian D. McMinn
- 👤 Gopi Ganapathy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/455; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
140 words
A method of simulating a hardware design having a plurality of level sensitive latches comprising providing a simulation circuit, the simulation circuit including a plurality of field programmable gate arrays and a plurality of edge triggered latches; providing a data signal to the simulation circuit; providing a system clock signal having a system clock signal frequency to the simulation circuit; generating a high frequency clock signal, the high frequency clock signal frequency having a frequency ratio to the system clock signal frequency which is greater than one; gating, using a field programmable gate array, the system clock signal with the high frequency signal to provide a high frequency enabled signal; providing the data signal to a data input of one of the edge sensitive latches; and clocking the one of the edge sensitive latches with the high frequency enabled signal.
Claim 2
Independent Claim
140 words
A method of simulating a hardware design having a plurality of level sensitive latches comprising providing a simulation circuit, the simulation circuit including a plurality of field programmable gate arrays and a plurality of edge triggered latches; providing a data signal to the simulation circuit; providing a system clock signal having a system clock signal frequency to the simulation circuit; generating a high frequency clock signal, the high frequency clock signal frequency having a frequency ratio to the system clock signal frequency which is greater than one; gating, using a field programmable gate array, the system clock signal with the high frequency signal to provide a high frequency enabled signal; providing the data signal to a data input of one of the edge sensitive latches; and clocking the one of the edge sensitive latches with the high frequency enabled signal.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the high frequency clock signal frequency is at least five times the system clock signal frequency.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the high frequency clock signal frequency is ten times the system clock signal frequency.
Claim 5
Dependent Claim
54 words
The method of claim 1 wherein the frequency ratio between the high frequency clock signal and the system clock signal provides a high frequency enabled signal which includes enough edges to accommodate the maximum number of level sensitive latches through which a signal passes during an active system clock signal of the hardware design.
Claim 6
Dependent Claim
34 words
The method of claim 1 further comprising determining the frequency ratio by dividing the time that the system clock signal is active in a period by the delay time of the level sensitive latches.
Claim 7
Independent Claim
125 words
An apparatus for simulating a hardware design having a plurality of level sensitive latches, the apparatus comprising: a field programmable gate array including a plurality of field programmable gates, at least one field programmable gate of the field programmable gate array coupled to receive a system clock signal having a first frequency and a high frequency clock signal having a second frequency greater than the first frequency, the at least one field programmable gate gating the system clock and the high frequency clock to provide a high frequency enabled signal; and a plurality of edge triggered latches, at least one of the edge triggered latches coupled to receive a data signal at a data input and the high frequency enabled signal at a clock input.
Claim 8
Independent Claim
125 words
An apparatus for simulating a hardware design having a plurality of level sensitive latches, the apparatus comprising: a field programmable gate array including a plurality of field programmable gates, at least one field programmable gate of the field programmable gate array coupled to receive a system clock signal having a first frequency and a high frequency clock signal having a second frequency greater than the first frequency, the at least one field programmable gate gating the system clock and the high frequency clock to provide a high frequency enabled signal; and a plurality of edge triggered latches, at least one of the edge triggered latches coupled to receive a data signal at a data input and the high frequency enabled signal at a clock input.
Claim 9
Dependent Claim
17 words
The apparatus of claim 6 wherein the second frequency is at least five times the first frequency.
Claim 10
Dependent Claim
15 words
The apparatus of claim 6 wherein the second frequency is ten times the first frequency.
Claim 11
Dependent Claim
52 words
The apparatus of claim 6 wherein the second and the first frequency are in a frequency ratio which provides a high frequency enabled signal which includes enough edges to accommodate the maximum number of level sensitive latches through which a signal passes during an active system clock signal of the hardware design.
Claim 12
Dependent Claim
41 words
The apparatus of claim 6 wherein the second and the first frequency are in a frequency ratio determined by dividing the time that the system clock signal is active in a period by the delay time of the level sensitive latches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |