US6025273A
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US
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Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask
Assignee: TSMC China Co Ltd
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Filing: 1998-04-06
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Granted: 2000-02-15
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Expires: 2018-04-06
Abstract
Abstract A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F + ) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O 2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.
Inventors
- 👤 Chao-Cheng Chen
- 👤 Chia-Shiung Tsai
- 👤 Hun-Jan Tao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:05
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/73; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/089; H10W20/40; H10W20/41; H10W20/42; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P76/00; H10P76/40; H10P76/405
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
238 words
A method for fabricating improved contact holes in an interlevel dielectric (ILD) layer on a semiconductor substrate for integrated circuits, comprising the steps of: providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer; depositing said interlevel dielectric (ILD) layer on said electrically conducting layer; depositing a polysilicon layer on said interlevel dielectric (ILD) layer; ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer; forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes; anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist; anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon atoms released from said carbon doped polysilicon layer during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said interlevel dielectric layer; removing said photoresist layer; annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer; blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes; cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching, and completing said interlevel dielectric (ILD) layer having said improved contact holes.
Claim 2
Independent Claim
238 words
A method for fabricating improved contact holes in an interlevel dielectric (ILD) layer on a semiconductor substrate for integrated circuits, comprising the steps of: providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer; depositing said interlevel dielectric (ILD) layer on said electrically conducting layer; depositing a polysilicon layer on said interlevel dielectric (ILD) layer; ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer; forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes; anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist; anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon atoms released from said carbon doped polysilicon layer during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said interlevel dielectric layer; removing said photoresist layer; annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer; blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes; cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching, and completing said interlevel dielectric (ILD) layer having said improved contact holes.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein the electrically conducting layer is composed of conductively doped polysilicon having a thickness of between about 2000 and 3000 Angstroms.
Claim 4
Dependent Claim
26 words
The method of claim 1, wherein said interlevel dielectric layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 6000 and 10000 Angstroms.
Claim 5
Dependent Claim
30 words
The method of claim 1, wherein said interlevel dielectric layer is silicon oxide (SiO 2 ) deposited by plasma enhance chemical vapor deposition using tetraethosiloxane (TEOS) as the reactant gas.
Claim 6
Dependent Claim
19 words
The method of claim 1, wherein said polysilicon layer has a thickness of between about 1000 and 2000 Angstroms.
Claim 7
Dependent Claim
41 words
The method of claim 5, wherein said polysilicon layer is ion implanted with carbon (C) at a dose of between 1.0 E 17 and 5.0 E 17 atoms/cm 2 and at a implant energy of between about 200 and 400 KeV.
Claim 8
Dependent Claim
32 words
The method of claim 1, wherein said openings in said carbon doped polysilicon layer are etched using reactive ion etching (RIE) and an etchant gas mixture composed of chlorine and hydrogen bromide.
Claim 9
Dependent Claim
53 words
The method of claim 1, wherein said contact holes in said interlevel dielectric layer are etched using a high density plasma (HDP) etcher and an etchant gas mixture composed of at least one of the group consisting of CF 4 , CHF 3 , C 2 F 6 , and C 4 F8.
Claim 10
Dependent Claim
24 words
The method of claim 1, wherein said annealing is carried out in an oxygen ambient at a temperature of at least 800 degrees centigrade.
Claim 11
Dependent Claim
39 words
The method of claim 1, wherein any said residual carbon atoms are removed from the surface of said silicon oxide using a solution of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ).
Claim 12
Independent Claim
243 words
A method for fabricating an interlevel dielectric (ILD) layer having improved metal plug contacts on a semiconductor substrate for integrated circuits, comprising the steps of: providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer; depositing said interlevel dielectric (ILD) layer on said electrically conducting layer; depositing a polysilicon layer on said interlevel dielectric (ILD) layer; ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer; forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes; anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist; anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon released from said carbon doped polysilicon layer, during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said insulating layer; removing said photoresist layer; annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer; blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes; cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching; depositing a barrier layer over and in said contact openings; forming metal plug contacts in said contact openings.
Claim 13
Independent Claim
243 words
A method for fabricating an interlevel dielectric (ILD) layer having improved metal plug contacts on a semiconductor substrate for integrated circuits, comprising the steps of: providing a semiconductor substrate having partially completed device structures including a patterned electrically conducting layer; depositing said interlevel dielectric (ILD) layer on said electrically conducting layer; depositing a polysilicon layer on said interlevel dielectric (ILD) layer; ion implanting carbon in said polysilicon layer to form a carbon doped polysilicon layer; forming a patterned photoresist layer having openings on said carbon doped polysilicon layer for said contact holes; anisotropic plasma etching openings in said carbon doped polysilicon layer to said interlevel dielectric (ILD) layer in said openings of said photoresist; anisotropically plasma etching using said carbon doped polysilicon layer as a hard mask to etch said contact openings in said interlevel dielectric layer to said electrically conducting layer, whereby said carbon released from said carbon doped polysilicon layer, during said etching, minimizes contamination buildup in said contact openings and increases the etch rate of said insulating layer; removing said photoresist layer; annealing in an oxidizing atmosphere and converting said polysilicon hard mask to a silicon oxide layer; blanket anisotropic plasma etching to remove any oxide formed on said conductive layer exposed in said contact holes; cleaning any residual carbon atoms from the surface of said silicon oxide layer by wet etching; depositing a barrier layer over and in said contact openings; forming metal plug contacts in said contact openings.
Claim 14
Dependent Claim
26 words
The method of claim 11, wherein the electrically conducting layer is composed of conductively doped polysilicon having a thickness of between about 2000 and 3000 Angstroms.
Claim 15
Dependent Claim
26 words
The method of claim 11, wherein said interlevel dielectric layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 6000 and 10000 Angstroms.
Claim 16
Dependent Claim
30 words
The method of claim 11, wherein said interlevel dielectric layer is silicon oxide (SiO 2 ) deposited by plasma enhanced chemical vapor deposition (PECVD) using tetraethosiloxane as the reactant gas.
Claim 17
Dependent Claim
19 words
The method of claim 11, wherein said polysilicon layer has a thickness of between about 1000 and 2000 Angstroms.
Claim 18
Dependent Claim
41 words
The method of claim 15, wherein said polysilicon layer is ion implanted with carbon (C) at a dose of between 1.0 E 17 and 5.0 E 17 atoms/cm 2 and at a implant energy of between about 200 and 400 KeV.
Claim 19
Dependent Claim
32 words
The method of claim 11, wherein said openings in said carbon doped polysilicon layer are etched using reactive ion etching (RIE) and an etchant gas mixture composed of chlorine and hydrogen bromide.
Claim 20
Dependent Claim
53 words
The method of claim 11, wherein said contact holes in said interlevel dielectric layer are etched using a high density plasma (HDP) etcher and an etchant gas mixture composed of at least one of the group consisting of CF 4 , CHF 3 , C 2 F 6 , and C 4 F8.
Claim 21
Dependent Claim
24 words
The method of claim 11, wherein said annealing is carried out in an oxygen ambient at a temperature of at least 800 degrees centigrade.
Claim 22
Dependent Claim
39 words
The method of claim 11, wherein any said residual carbon atoms are removed from the surface of said silicon oxide using a solution of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ).
Claim 23
Dependent Claim
24 words
The method of claim 11, wherein said barrier layer is titanium nitride (TiN) and has a thickness of between about 400 and 900 Angstroms.
Claim 24
Dependent Claim
40 words
The method of claim 11, wherein said metal plug contacts are composed of tungsten (W) and are formed by depositing a tungsten film sufficient to fill the contact holes and is then blanket etched back to the silicon oxide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |