DRAM cell with a rugged stacked trench (RST) capacitor

Claim 2

Trench capacitors formed in a semiconductor substrate, said capacitors comprising: trenches formed in said semiconductor substrate; first storage nodes including doped ion regions and doped polysilicon structures having a rugged surface formed on the entire surface of said trench to increase a surface area, said doped regions being formed in a surface of said trenches, said doped polysilicon structures being formed on side walls of said trenches; an isolation structure formed on said substrate between said trenches for isolation; a dielectric layer substantially covering said first storage nodes; a field plate formed on said isolation structure; and second storage nodes formed in said trenches and on said dielectric layer.

Claim 3

The capacitors of claim 1, wherein said doped polysilicon structures are chosen from the group consisting of doped polysilicon and in-situ doped polysilicon.

Claim 4

The capacitors of claim 1, wherein said dielectric layer is formed of Ta 2 O 5 .

Claim 5

The capacitors of claim 1, wherein said dielectric layer is formed of BST.

Claim 6

The capacitors of claim 1, wherein said dielectric layer is formed of PZT.

Claim 7

The capacitors of claim 1, wherein said dielectric layer is a triple film of silicon oxide, silicon nitride, silicon oxide.

Claim 8

The capacitors of claim 1, wherein said dielectric layer is a double film of silicon nitride, silicon oxide film.

Claim 9

The capacitors of claim 1, wherein said second storage node is chosen from the group consisting of doped polysilicon and in-situ doped polysilicon.

Claim 10

The capacitors of claim 1, wherein said second storage node is chosen from the group consisting of metal and alloy.

Claim 11

Trench DRAM cells formed in a semiconductor substrate, said capacitors comprising: trenches formed in said semiconductor substrate; first storage nodes including doped ion regions and doped polysilicon structures having a rugged surface formed on the entire surface of said trench to increase a surface area, said doped regions being formed in a surface of said trenches, said doped polysilicon structures being formed on side walls of said trenches; an isolation structure formed on said substrate between said trenches for isolation; a dielectric layer substantially covering said first storage nodes; a field plate formed on said isolation structure; second storage nodes formed in said trenches and on said dielectric layer; and at least one transistor formed on said semiconductor substrate and being connected to said doped ion region.

Claim 12

Trench DRAM cells formed in a semiconductor substrate, said capacitors comprising: trenches formed in said semiconductor substrate; first storage nodes including doped ion regions and doped polysilicon structures having a rugged surface formed on the entire surface of said trench to increase a surface area, said doped regions being formed in a surface of said trenches, said doped polysilicon structures being formed on side walls of said trenches; an isolation structure formed on said substrate between said trenches for isolation; a dielectric layer substantially covering said first storage nodes; a field plate formed on said isolation structure; second storage nodes formed in said trenches and on said dielectric layer; and at least one transistor formed on said semiconductor substrate and being connected to said doped ion region.

Claim 13

The capacitors of claim 10, wherein said doped polysilicon structures are chosen from the group of doped polysilicon and in-situ doped polysilicon.

Claim 14

The capacitors of claim 10, wherein said dielectric layer is formed of Ta 2 O 5 .

Claim 15

The capacitors of claim 10, wherein said dielectric layer is formed of BST.

Claim 16

The capacitors of claim 10, wherein said dielectric layer is formed of PZT.

Claim 17

The capacitors of claim 10, wherein said dielectric layer is a triple film of silicon oxide, silicon nitride, silicon oxide.

Claim 18

The capacitors of claim 10, wherein said dielectric layer is a double film of silicon nitride, silicon oxide film.

Claim 19

The capacitors of claim 10, wherein said second storage node is chosen from the group consisting of doped polysilicon and in-situ doped polysilicon.

Claim 20

The capacitors of claim 10, wherein said second storage node is chosen from the group consisting of metal and alloy.