Semiconductor memory device with trench capacitor

Claim 1

A memory matrix, comprising at least four memory cells of a semiconductor memory configuration in a semiconductor substrate having bit lines and word lines, each of said memory cells including: a given width, one trench memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode, each memory capacitor being connected to one of said conducting regions of a transistor, the other of said conducting regions of said transistor being connected to one of said bit lines, and said gate electrode of said transistor being connected to one of said word lines, an insulating oxide region having substantially vertical side walls, a trench adjacent to said insulating oxide region and adjacent to one of said conducting regions without surrounding said conducting regions, said trench having an inner trench wall surface and a trench bottom, and said capacitors each being disposed in one trench for each memory cell, a first insulating layer completely covering said inner trench wall surface and said trench bottom, a first electrode of the capacitor disposed perpendicular to the substrate surface on said first insulating layer completely inside said trench, a second insulating layer disposed on said first electrode and on said trench bottom, a second electrode disposed vertically on said second insulating layer in said trench, and a contact defined by a small opening formed in said first insulating layer on one side of said inner trench wall, said contact directly connecting said first electrode of said capacitor and one of said conducting regions of said transistor laterally through an opening formed in said first insulating layer on said inner trench wall surface; said capacitor and said conducting region defining an imaginary line therebetween, a first direction being parallel to said line and a second direction being perpendicular to said first direction, two successive cells being disposed in mirror symmetry with an axis of symmetry extending perpendicularly to said first direction centrally between two successive cells; and each of said memory cells being offset by one-half said given cell width in said second direction.