Process for manufacturing semiconductor memory device and product formed thereby

Claim 2

A semiconductor integrated circuit device equipped with memory cells, each memory cell comprising a series circuit of a capacitor and an MISFET, the MISFET having source and drain regions, each said capacitor comprising: a moat in a surface of a semiconductor substrate, wherein said moat is adjacent to, but does not surround, said a first electrode annularly formed on the side wall surface of said moat; a first semiconductor region in said semiconductor substrate which is formed along the entire periphery of the side wall surface of the upper end portion of said moat and connected to said first electrode; a first insulator film formed on said first electrode; and a second electrode formed on said first insulator film, wherein one of the source and drain regions of said MISFET is connected to said first semiconductor region, whereby said one of the source and drain regions of said MISFET is connected to said first electrode via said first semiconductor region.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said source and drain regions of said MISFET are formed in said semiconductor substrata.

Claim 4

A semiconductor integrated circuit device according to claim 1, further comprising a second insulator film formed between said first electrode and said semiconductor substrate, and formed on the bottom of said moat.

Claim 5

A semiconductor integrated circuit device according to claim 1, wherein said moat is substantially rectangular in a plan view of said semiconductor substrate.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein a direction extending from one of the source and drain regions of said MISFET to another of the source and drain regions of said MISFET is substantially perpendicular to the long side of said rectangle of said moat, and one of the source and drain regions of said MISFET is connected to said first semiconductor region at a substantially central portion of said long side of said rectangle.

Claim 7

A semiconductor integrated circuit device according to claim 1, further comprising a field insulating film for electrically isolating memory cells from each other, and a channel stopper region under the field insulating film, and wherein said first semiconductor region does not extend to a greater depth than does the channel stopper region.

Claim 8

A semiconductor integrated circuit device according to claim 1, wherein the first semiconductor region includes phosphorus as an impurity ion.

Claim 9

A semiconductor integrated circuit device according to claim 1, wherein said memory cells comprise a plurality of memory cells whereby a plurality of moats are provided in said substrate; and wherein said moats are positioned such that a portion of a moat of one memory cell is located between moats of adjacent cells.

Claim 10

A semiconductor integrated circuit device according to claim 1, wherein said memory cells comprise a plurality of memory cells, whereby a plurality of moats are provided in said substrate; and wherein adjacent memory cells are positioned such that the MISFETS of adjacent memory cells are located between the moats of said memory cells.

Claim 11

A semiconductor integrated circuit device according to claim 9, wherein the MISFETS of adjacent memory cells share a common semiconductor region for said source of drain region, the common semiconductor region being the source of drain region other than said one of the source and drain regions.

Claim 12

A semiconductor integrated circuit device according to claim 1, wherein the MISFETS of adjacent memory cells share a common semiconductor region for said source or drain region, the common semiconductor region being the source or drain region other than said one of the source and drain regions.

Claim 13

A semiconductor integrated circuit device according to claim 1, further comprising a second semiconductor region in the substrate, extending from the surface of the substrate exposed in the moat, from a location under the first semiconductor region, the second semiconductor region being of conductivity type different from that of the first semiconductor region, the second semiconductor region being employed as the other electrode of said capacitor; a dielectric film, for a second capacitor, formed on a surface of the first electrode; and a further conductive layer formed on the dielectric film so as to form a second capacitor, whereby two capacitors can be formed using a single moat.

Claim 14

A semiconductor integrated circuit device equipped with memory cells, each memory cell comprising a series circuit of a capacitor and an MISFET, the MISFET having source and drain regions, each said capacitor comprising: a moat in a surface of a semiconductor substrate; a first electrode annularly formed on the side wall surface of said moat; a first semiconductor region in said semiconductor substrate which is formed along the entire periphery of the side wall surface of the upper end portion of said moat and connected to said first electrode; a first insulator film formed on said first electrode; a second electrode formed on said first insulator film, wherein one of the source and drain regions of said MISFET is connected to said first semiconductor region, whereby said one of the source and drain regions of said MISFET is connected to said first electrode via said first semiconductor region; a second semiconductor region in the substrate, extending from the surface of the substrate exposed in the moat, from a location under the first semiconductor region, the second semiconductor region being of conductivity type different from that of the first semiconductor region, the second semiconductor region being employed as the other electrode of said capacitor; a dielectric film, for a second capacitor, formed on a surface of the first electrode; and a further conductive layer formed on the dielectric film so as to form a second capacitor, whereby two capacitors can be formed using a single moat.

Claim 15

A semiconductor integrated circuit device equipped with memory cells, each memory cell comprising a series circuit of a capacitor and an MISFET, the MISFET having source and drain regions, each said capacitor comprising: a moat in a surface of a semiconductor substrate; a first electrode annularly formed on the side wall surface of said moat; a first semiconductor region in said semiconductor substrate which is formed along the entire periphery of the side wall surface of the upper end portion of said moat and connected to said first electrode; a first insulator film formed on said first electrode; a second electrode formed on said first insulator film, wherein one of the source and drain regions of said MISFET is connected to said first semiconductor region, whereby said one of the source and drain regions of said MISFET is connected to said first electrode via said first semiconductor region; a second semiconductor region in the substrate, extending from the surface of the substrate exposed in the moat, from a location under the first semiconductor region, the second semiconductor region being of conductivity type different from that of the first semiconductor region, the second semiconductor region being employed as the other electrode of said capacitor; a dielectric film, for a second capacitor, formed on a surface of the first electrode; and a further conductive layer formed on the dielectric film so as to form a second capacitor, whereby two capacitors can be formed using a single moat.