US5124765A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Highly integrated semiconductor memory device with trench capacitors and stacked capacitors
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-01-04
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Granted: 1992-06-23
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Expires: 2011-01-04
Abstract
Abstract A highly integrated semiconductor memory device comprises a plurality of memory cells formed by alternately disposing a stack-type capacitor cell and a combined stack-trench type capacitor cell both in row and column directions. Each storage electrode of the capacitor of the memory cell is extended to overlap with the storage electrode of the capacitor of the adjacent memory cell. The combined stack-trench type capacitor is formed into the substrate to increase the storage capacitance thereof which allow the storage capacitance of the stack-type capacitor to increase by extending the storage electrode of the capacitor. Due to the alternate arrangement of stack-trench type capacitor and stack-type capacitor, step coverage, leakage current and soft errors of stack-trench type capacitor are prevented.
Inventors
- 👤 Seong-tae Kim
- 👤 Kyung-hun Kim
- 👤 Jae-hong Ko
- 👤 Su-han Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:10
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377; H10B12/31; H10B12/318; H10P; H10P14/00; H10P14/20; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3416; H10P14/3424; H10P14/3426; H10P95/00; H10P95/04; H10W; H10W20/00; H10W20/01; H10W20/031
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
182 words
A highly integrated semiconductor memory device comprising: first and second pluralities of memory cells, each memory cell in said first plurality of memory cells including a first switching transistor formed on a semiconductor substrate and a first capacitor coupled to said first switching transistor, each memory cell in said second plurality of memory cells including a second switching transistor formed on a semiconductor substrate and a second capacitor coupled to said second switching transistor, and each of said first and second memory cells alternately disposed in each of a plurality of rows, each first capacitor in each memory cell of said first plurality of memory cells further comprising: a first storage electrode including a trench portion formed partially in said substrate and a first stack portion overlapping a portion of said adjacent second memory cell; and each second capacitor in each memory cell of said second plurality of memory cells further comprising: a second storage electrode including only a second stack portion overlapping a portion of said adjacent first memory cell and not including a trench portion formed partially in said substrate.
Claim 2
Dependent Claim
182 words
A highly integrated semiconductor memory device comprising: first and second pluralities of memory cells, each memory cell in said first plurality of memory cells including a first switching transistor formed on a semiconductor substrate and a first capacitor coupled to said first switching transistor, each memory cell in said second plurality of memory cells including a second switching transistor formed on a semiconductor substrate and a second capacitor coupled to said second switching transistor, and each of said first and second memory cells alternately disposed in each of a plurality of rows, each first capacitor in each memory cell of said first plurality of memory cells further comprising: a first storage electrode including a trench portion formed partially in said substrate and a first stack portion overlapping a portion of said adjacent second memory cell; and each second capacitor in each memory cell of said second plurality of memory cells further comprising: a second storage electrode including only a second stack portion overlapping a portion of said adjacent first memory cell and not including a trench portion formed partially in said substrate.
Claim 3
Dependent Claim
43 words
A highly integrated semiconductor memory device as claimed in claim 1, wherein said first plurality of memory cells and said second plurality of memory cells are disposed alternately and adjacently both in each of said plurality of rows and in a column direction.
Claim 4
Dependent Claim
35 words
A highly integrated semiconductor memory device as claimed in claim 1, wherein said trench portion formed partially in said substrate of each first capacitor has a depth in the range of about 0.5 μm˜10 μm.
References Cited (Backward Citations)
JPS62137863A
Cited
US4974040A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |