Patent US6011741A successfully refreshed from Google Patents.
US6011741A
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Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
Assignee: SanDisk Technologies LLC
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Filing: 1998-07-23
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Granted: 2000-01-04
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Expires: 2018-07-23
Abstract
Abstract A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.
Inventors
- 👤 Robert F. Wallace
- 👤 Robert D. Norman
- 👤 Eliyahou Harari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:10
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K19/077; G06K19/0772; G06K19/07732; G06K19/07737; G06K19/07741; G06K19/07743; G06K7/00; G06K7/0013; G06K7/0047; G11; G11C; G11C5/00; G11C5/02; G11C5/04; H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H05K7/00; H05K7/14; H05K7/1422; H05K7/1427; H05K7/1429; H05K7/1431; G06F3/0628; G06F3/0662; G06F3/0664; H05K2201/00; H05K2201/10; H05K2201/10007; H05K2201/10159; H05K2201/10431; H05K2201/10439; H05K2201/10462; H05K2201/10484; H05K2203/00; H05K2203/15; H05K2203/1572; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H10; H10W; H10W72/00; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
269 words
A non-volatile memory system adapted for use with a host system, comprising: a memory controller having a connector to receive a memory card and connectable to (1) receiving address, user data and command signals from said host system according to a given protocol and (2) providing user data and status signals to said host system according to said given protocol, said controller including at least one microprocessor that executes commands from the host system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the controller connector, a plurality of said memory cards which individually include a card connector that mechanically mates with the controller connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters, said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said controller and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said controller connector, and a serial communications circuit extending through the controller and memory card connectors to transfer user data between the buffer memory of said controller and said at least one accessed memory cell group.
Claim 2
Dependent Claim
269 words
A non-volatile memory system adapted for use with a host system, comprising: a memory controller having a connector to receive a memory card and connectable to (1) receiving address, user data and command signals from said host system according to a given protocol and (2) providing user data and status signals to said host system according to said given protocol, said controller including at least one microprocessor that executes commands from the host system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the controller connector, a plurality of said memory cards which individually include a card connector that mechanically mates with the controller connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters, said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said controller and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said controller connector, and a serial communications circuit extending through the controller and memory card connectors to transfer user data between the buffer memory of said controller and said at least one accessed memory cell group.
Claim 3
Dependent Claim
209 words
The memory system according to claim 1, wherein said memory controller further includes: a plurality of temporary storage registers, including at least one set for storing a storage block address received from the host system, a command register and a status register, means for allowing the host system to write a storage block address to said one register set, to write a command to the command register, to read a status from the status register, to write user data into the buffer memory and to read user data from the buffer memory, means including the microprocessor for reading from said one register set the address stored from the host system and translating said host system address into an address of one or more memory cell groups corresponding to the host system address, and means including the microprocessor for reading the command register and (1) in response to a read command, transferring user data within the addressed at least one memory cell group into the buffer memory and then write a completion status in the status register, or (2) in response to a write command, transferring user data from the buffer memory into the addressed at least one memory cell group and write a completion status into the status register.
Claim 4
Dependent Claim
48 words
The memory system according to claim 1 wherein said memory system includes a second controller connector to receive and connect the card connector of another of the plurality of said memory cards, thereby to establish operation of the controller simultaneously with two of said plurality of memory cards.
Claim 5
Dependent Claim
43 words
The memory system according to claim 1 wherein individual ones of the groups of memory cells that are simultaneously erasable include enough cells to store 512 bytes of user data plus overhead data related to a sector and the user data stored therein.
Claim 6
Dependent Claim
149 words
The memory system according to claim 1, wherein the memory cards individually include: a plurality of sub-boards each carrying a plurality of flash EEPROM integrated circuit chips and including electrical conductors attached thereto which interconnect said chips to a plurality of electrical contacts along one edge of said sub-board, said contacts having a predetermined pattern therealong, a main circuit board including electrical conductors attached thereto and extending between (a) a plurality of rows of electrical contacts on at least one side thereof that are each arranged in said pattern and (b) a plurality of electrical contacts at an edge thereof positioned to form part of a connector, said sub-boards being attached to said main board with their edge contacts being electrically connected to respective ones of said plurality of rows of contacts on the main board, and a cover enclosing said main printed circuit board and the attached sub-boards.
Claim 7
Dependent Claim
27 words
The memory system according to any one of claims 1-3, wherein the controller additionally includes another connector for removable mechanical and electrical connection with the host system.
Claim 8
Dependent Claim
21 words
The memory system according to claim 6 wherein said another controller connector includes conductors conforming to an industry standard IDE interface.
Claim 9
Dependent Claim
37 words
The memory system according to any one of claims 1-3, wherein the memory cells of the integrated circuit array are individually programmable into exactly two states in order to store exactly one bit of data per cell.
Claim 10
Dependent Claim
39 words
The memory system according to any one of claims 1-3, wherein the memory cells of the integrated circuit array are individually programmable into more than two states in order to store more than one bit of data per cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-03 | 2003-07-05 | 2004-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-03 | 2007-07-05 | 2008-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-03 | 2011-07-05 | 2012-01-04 | $7700.00 | Window Closed / Lapsed |