US5033027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial DRAM controller with multi generation interface
Assignee: Dallas Semiconductor Corp
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Filing: 1990-01-19
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Granted: 1991-07-16
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Expires: 2010-01-19
Abstract
Abstract A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.
Inventors
- 👤 Pravin T. Amin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/406
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
162 words
An integrated circuit dynamic memory controller, comprising: a serial port interface configured for interface to a serial data bus which includes a reset line, a clock line, and at least one data line; refresh control signal generation logic connected to provide a refresh control signal output to one or more dynamic memories, said logic output in response to transitions of said clock line as follows: each transition of said clock line from a first state to a second state is followed by an active cycle of the dynamic memories for a predetermined time period which is then followed by refresh cycles of the dynamic memories until a transition of said clock line from said second state back to said first state, and each transition of said clock line from said second state to said first state is followed by a refresh cycle of the dynamic memories until a transition of said clock line from said first state back to said second state.
Claim 2
Dependent Claim
162 words
An integrated circuit dynamic memory controller, comprising: a serial port interface configured for interface to a serial data bus which includes a reset line, a clock line, and at least one data line; refresh control signal generation logic connected to provide a refresh control signal output to one or more dynamic memories, said logic output in response to transitions of said clock line as follows: each transition of said clock line from a first state to a second state is followed by an active cycle of the dynamic memories for a predetermined time period which is then followed by refresh cycles of the dynamic memories until a transition of said clock line from said second state back to said first state, and each transition of said clock line from said second state to said first state is followed by a refresh cycle of the dynamic memories until a transition of said clock line from said first state back to said second state.
Claim 3
Dependent Claim
52 words
The controller of claim 1, wherein, if one of said transitions of said clock line from said second state to said first state is not promptly followed by one of said transitions of said clock line from said first state to said second state, multiple ones of said refresh cycles will occur.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |