Ball grid array semiconductor package with solder ball openings in an insulative base

Claim 2

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material; respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; and wherein conductive bumps connect the semiconductor chip to the first pads and the solder balls are connected to the solder ball pads, and wherein the diameter of the bumps to be attached to the first pads on the second surface of the insulative base is larger than that of the bumps to be attached to the first pads on the first surface of the insulative base, in order to compensate for the thickness of the insulative base material.

Claim 3

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material; respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface and, in which the first openings are filled by a conductive filler to compensate for the thickness of the insulative base material; and in which the conductive filler is a conductive resin or a plating layer.

Claim 4

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material; respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface and, in which the first openings are filled by a conductive filler to compensate for the thickness of the insulative base material; and in which the conductive filler is a conductive resin or a plating layer.

Claim 5

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and in which the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than that of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material.

Claim 6

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and in which the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than that of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material.

Claim 7

The area grid array package of claim 1 wherein the insulative base material and the semiconductor chip are attached to a heat slug.

Claim 8

The area grid array package of claim 1 in which the second openings for connecting to the semiconductor chip are formed from the first surface so that the openings reach to the first pads on the second surface.

Claim 9

The area grid array package of claim 1 in which the first and second openings are laser-formed openings.

Claim 10

The area gird array package of claim 1 in which the insulative base material is a rigid panel.

Claim 11

The area grid array package of claim 1 in which the insulative base material is a flexible film or a tape.

Claim 12

The area grid array package of claim 1 in which the openings leading to the solder ball pads are filled by a conductive filler to compensate for the thickness of the insulative base material.

Claim 13

The area grid array package of claim 1 in which the openings leading to the first pads are filled by a conductive filler to compensate for the thickness of the base material.

Claim 14

The area grid array package of claim 10 in which the conductive filler is a conductive resin.

Claim 15

A ball grid array semiconductor package comprising: an insulative base material; circuitry metallizations formed on a first surface and a second surface of the insulative base material the second surface being opposite to the first surface, each circuitry metallization having a first connection pad adjacent one end and a second bonding pad adjacent a second end; a semiconductor chip mounted adjacent to said first surface and said first connection pads, said chip being electrically connected to said first connection pads of the circuitry metallizations; wherein the insulative base material has first openings extending from the second surface of the insulative base material at a location under second bonding pads; wherein each of said first openings confines a portion of a solder ball which is in a solder melt-fixed connection to a facing side of each said second bonding pads, wherein said first openings are in the second surface of the insulative base material and said second openings are either the first or the second surfaces of the insulative base material; and wherein said second openings are in the first surface and wherein solder balls extend from said chip to connection pads on the first surface and through said second openings to connection pads on said second surface.

Claim 16

A ball grid array semiconductor package comprising: an insulative base material; circuitry metallizations formed on a first surface and a second surface of the insulative base material the second surface being opposite to the first surface, each circuitry metallization having a first connection pad adjacent one end and a second bonding pad adjacent a second end; a semiconductor chip mounted adjacent to said first surface and said first connection pads, said chip being electrically connected to said first connection pads of the circuitry metallizations; wherein the insulative base material has first openings extending from the second surface of the insulative base material at a location under second bonding pads; wherein each of said first openings confines a portion of a solder ball which is in a solder melt-fixed connection to a facing side of each said second bonding pads, wherein said first openings are in the second surface of the insulative base material and said second openings are either the first or the second surfaces of the insulative base material; and wherein said second openings are in the first surface and wherein solder balls extend from said chip to connection pads on the first surface and through said second openings to connection pads on said second surface.

Claim 17

The ball grid array semiconductor package as defined in claim 12 wherein the insulative base material is a film or a sheet.

Claim 18

The ball grid array semiconductor package as defined in claim 12 wherein the insulative base material is a reinforced laminate.

Claim 19

The ball grid array package as defined in claim 12 wherein said insulative base material and said chip are adhesively mounted to a heat slug.

Claim 20

The ball grid array package as defined in claim 12 wherein a conductive filler is included within said first openings.

Claim 21

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material; respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than the diameter of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material; and wherein a correspondingly large diameter opening is provided in the insulative base material to confine the larger diameter solder balls.

Claim 22

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material; respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than the diameter of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material; and wherein a correspondingly large diameter opening is provided in the insulative base material to confine the larger diameter solder balls.

Claim 23

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and in which the opening leading to the first pads is filled with a conductive filler to compensate for the thickness of the base material and the conductive filler is a conductive resin.

Claim 24

An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and in which the opening leading to the first pads is filled with a conductive filler to compensate for the thickness of the base material and the conductive filler is a conductive resin.

Claim 25

The area grid array package of claim 18 wherein conductive bumps connect the semiconductor chip to the first pads and the solder balls are connected to the solder ball pads, and wherein the diameter of the bumps to be attached to the first pads on the second surface of the insulative base is larger than that of the bumps to be attached to the first pads on the first surface of the insulative base, in order to compensate for the thickness of the insulative base material.