High-order multipath operational amplifier with dynamic offset reduction, controlled saturation current limiting, and current feedback for enhanced conditional stability

Claim 2

An amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path from the signal input to the signal output for bypassing a first one of the integrator stages in the low-frequency path; wherein the first one of the integrator stages includes a differential amplifier and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages.

Claim 3

The amplifier as claimed in claim 1, wherein the dynamic offset reduction circuit includes at least one chopper for chopper-stabilizing the differential amplifier.

Claim 4

The amplifier as claimed in claim 1, wherein the dynamic offset reduction circuit has a clock input for accepting at least one clock signal and produces undesirable artifacts from said clock signal, and further including an analog low-pass filter connected to the first one of the integrator stages to prevent the undesirable artifacts from passing from the first one of the integrator stages to the signal output.

Claim 5

The amplifier as claimed in claim 3, wherein the analog low-pass filter is inserted into the low-frequency path between the first one of the integrator stages and the second one of the integrator stages, and the analog low-pass filter introduces substantial attenuation into the low-frequency path at zero frequency.

Claim 6

The amplifier as claimed in claim 4, wherein the analog low-pass filter includes a differential amplifier having differential outputs and a gain substantially less than one, and capacitance shunting the differential outputs.

Claim 7

The amplifier as claimed in claim 4, wherein the relatively high-frequency bypass path includes the second one of the integrator stages, and the analog low-pass filter has a 3-dB cutoff frequency no less than a frequency at which signal gain through the low-frequency path from the signal input to the second one of the integrator stages is equal to signal gain through the relatively high-frequency bypass path from the signal input to the second one of the integrator stages.

Claim 8

The amplifier as claimed in claim 3, wherein the analog low-pass filter is inserted into the low-frequency path between the first one of the integrator stages and the second one of the integrator stages, the relatively high-frequency bypass path includes the second one of the integrator stages but does not include the analog low-pass filter, and further including an intermediate bypass path from the signal output to the analog low-pass filter for additional bypassing of the first integrator stage.

Claim 9

The amplifier as claimed in claim 3, wherein the relatively high-frequency bypass path extends from the signal input to a last one of the integrator stages in the low-frequency path and bypasses all of the integrator stages in the low-frequency path except for the last one of the integrator stages in the low-frequency path.

Claim 10

The amplifier as claimed in claim 1, further comprising a feedback path to an input of one of the integrators in the low-frequency path from an output of an integrator in the low-frequency path immediately following said one of the integrators in the low-frequency path.

Claim 11

The amplifier as claimed in claim 1, wherein the low-frequency path and the relatively high-frequency path converge at a current summing node combining current from a current source in the low-frequency path with current from a current source in the relatively high-frequency path, the current source in the relatively high-frequency path having a first saturation current limit, and the current source in the low-frequency path having a second saturation current limit, wherein the first and second saturation current limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

Claim 12

The amplifier as claimed in claim 10, wherein the current source in the relatively high-frequency path is a first differential amplifier having a common mode current having a magnitude substantially equal to the first saturation current limit, and the current source in the low-frequency path is a second differential amplifier having a common mode current having a magnitude substantially equal to the second saturation current limit.

Claim 13

The amplifier as claimed in claim 10, wherein the current source in the relatively high-frequency path is a first field-effect transistor, the current source in the low-frequency path is a second field-effect transistor, and the first field-effect transistor has a substantially higher transconductance than the second field-effect transistor.

Claim 14

The amplifier as claimed in claim 1, further including a current feedback input, and wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented at the current feedback input.

Claim 15

The amplifier as claimed in claim 13, wherein the relatively high-frequency path includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current flow through the resistance presented at the current feedback input.

Claim 16

The amplifier as claimed in claim 14, wherein the controlled voltage source is a transistor follower circuit having a voltage follower output at the current feedback input.

Claim 17

The amplifier as claimed in claim 13, further including a voltage feedback input substantially independent of the current feedback input, the voltage feedback input providing voltage feedback to a first one of the integrator stages in the low-frequency path, and the current feedback input providing current feedback to an output stage in the relatively high-frequency path.

Claim 18

A conditionally-stable multipath operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path from the signal input to a last one of the integrator stages in the low-frequency path; and an intermediate bypass path from the signal input to a second one of the integrator stages in the low-frequency path for bypassing a first one of the integrator stages in the relatively low-frequency path; wherein the first one of the integrator stages includes a differential amplifier and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages; and further comprising an analog low-pass filter in the low-frequency path between the differential amplifier and the second one of the integrator stages to prevent artifacts of dynamic offset reduction from reaching the second one of the integrator stages.

Claim 19

A conditionally-stable multipath operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path from the signal input to a last one of the integrator stages in the low-frequency path; and an intermediate bypass path from the signal input to a second one of the integrator stages in the low-frequency path for bypassing a first one of the integrator stages in the relatively low-frequency path; wherein the first one of the integrator stages includes a differential amplifier and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages; and further comprising an analog low-pass filter in the low-frequency path between the differential amplifier and the second one of the integrator stages to prevent artifacts of dynamic offset reduction from reaching the second one of the integrator stages.

Claim 20

The conditionally-stable multipath operational amplifier as claimed in claim 17, wherein the analog low-pass filter introduces substantial attenuation into the low-frequency path at zero frequency.

Claim 21

The conditionally-stable multipath operational amplifier as claimed in claim 17, wherein the analog low-pass filter is at least a third-order analog low-pass filter.

Claim 22

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein the low-frequency path and the relatively high-frequency path converge at a current summing node combining current from a current source in the low-frequency path with current from a current source in the relatively high-frequency path, the current source in the relatively high-frequency path having a first saturation current limit, the current source in the low-frequency path having a second saturation current limit, and the first and second saturation current limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

Claim 23

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein the low-frequency path and the relatively high-frequency path converge at a current summing node combining current from a current source in the low-frequency path with current from a current source in the relatively high-frequency path, the current source in the relatively high-frequency path having a first saturation current limit, the current source in the low-frequency path having a second saturation current limit, and the first and second saturation current limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

Claim 24

The conditionally-stable operational amplifier as claimed in claim 20, wherein the second saturation current limit is substantially less than the first saturation current limit.

Claim 25

The conditionally-stable operational amplifier as claimed in claim 20, wherein the current source in the relatively high-frequency path is a first differential amplifier having a common mode current having a magnitude substantially equal to the first saturation current limit, and the current source in the low-frequency path is a second differential amplifier having a common mode current having a magnitude substantially equal to the second saturation current limit.

Claim 26

The conditionally-stable operational amplifier as claimed in claim 20, wherein the current source in the relatively high-frequency path is a first field-effect transistor, the current source in the low-frequency path is a second field-effect transistor, and the first field-effect transistor has a substantially higher transconductance than the second field-effect transistor.

Claim 27

The conditionally-stable operational amplifier as claimed in claim 20, further including a current feedback input, wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented at the current feedback input.

Claim 28

The conditionally-stable operational amplifier as claimed in claim 24, wherein the relatively high-frequency path includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current through the resistance presented at the current feedback input.

Claim 29

The conditionally-stable operational amplifier as claimed in claim 25, wherein the controlled voltage source is a transistor follower circuit having a voltage follower output at the current feedback input.

Claim 30

The conditionally-stable operational amplifier as claimed in claim 20, further comprising a feedback path to an input of one of the integrators in the low-frequency path from an output of an integrator in the low-frequency path immediately following said one of the integrators in the low-frequency path.

Claim 31

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, wherein the conditionally-stable operational amplifier has an open-loop unity gain frequency for unity gain from said signal input to said signal output, the conditionally-stable operational amplifier has at least 180 degrees of phase lag from said signal input to said signal output for a frequency less than the open-loop unity gain frequency, and the phase lag from said signal input to said signal output decreases to less than 180 degrees as frequency increases to the open-loop unity gain frequency.

Claim 32

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, wherein the conditionally-stable operational amplifier has an open-loop unity gain frequency for unity gain from said signal input to said signal output, the conditionally-stable operational amplifier has at least 180 degrees of phase lag from said signal input to said signal output for a frequency less than the open-loop unity gain frequency, and the phase lag from said signal input to said signal output decreases to less than 180 degrees as frequency increases to the open-loop unity gain frequency.

Claim 33

The conditionally-stable operational amplifier as claimed in claim 28, further including a controlled voltage source in the signal path for applying a voltage to the current feedback input in response to an input signal on the signal input.

Claim 34

The conditionally-stable operational amplifier as claimed in claim 29, wherein the controlled voltage source includes a differential amplifier having a feedback input connected to the current feedback input so that the controlled voltage source applies to the current feedback input a voltage responsive to a difference between the input signal on the signal input and the voltage applied to the current feedback input.

Claim 35

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, further including a controlled voltage source in the signal path for applying a voltage to the current feedback input in response to an input signal on the signal input, and wherein the conditionally-stable operational amplifier includes a low-frequency path from the signal input to the controlled voltage source, the low-frequency path includes a series of at least two integrator stages connected between the signal input and the controlled voltage source, and the conditionally-stable operational amplifier further includes a relatively high-frequency bypass path from the signal input to the controlled voltage source for bypassing said at least two integrator stages.

Claim 36

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, further including a controlled voltage source in the signal path for applying a voltage to the current feedback input in response to an input signal on the signal input, and wherein the conditionally-stable operational amplifier includes a low-frequency path from the signal input to the controlled voltage source, the low-frequency path includes a series of at least two integrator stages connected between the signal input and the controlled voltage source, and the conditionally-stable operational amplifier further includes a relatively high-frequency bypass path from the signal input to the controlled voltage source for bypassing said at least two integrator stages.

Claim 37

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, and wherein the conditionally-stable operational amplifier includes a low frequency path from the signal input to the signal output, the low-frequency path includes at least one integrator stage connected between the signal input and the controlled voltage source, and said at least one integrator stage includes a voltage feedback input substantially independent of said current feedback input.

Claim 38

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, and wherein the conditionally-stable operational amplifier includes a low frequency path from the signal input to the signal output, the low-frequency path includes at least one integrator stage connected between the signal input and the controlled voltage source, and said at least one integrator stage includes a voltage feedback input substantially independent of said current feedback input.

Claim 39

The conditionally-stable operational amplifier as claimed in claim 32, further including a first feedback circuit connected from said signal output to said voltage feedback input, and a second feedback circuit connected from said signal output to said current feedback input.

Claim 40

The conditionally-stable operational amplifier as claimed in claim 33, wherein said first feedback circuit and said second feedback circuit are adjustable and are coupled for adjustment of feedback of said second feedback circuit from said signal input to said current feedback input substantially in proportion to adjustment of feedback of said first feedback circuit from said signal input to said voltage feedback input.

Claim 41

The conditionally-stable operational amplifier as claimed in claim 29, wherein the controlled voltage source includes a transistor in a voltage follower stage, said current received at the current feedback input passing through said transistor in a path to the output stage.

Claim 42

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, wherein the output stage asserts a voltage on the signal output in proportion to current received at the current feedback input, the conditionally-stable operational amplifier has a unity gain frequency for unity gain from said signal input to said signal output, and wherein the conditionally-stable operational amplifier has a transimpedance from the current input to the signal output that has a phase lag of more than 180 degrees from the current output to the current input for a frequency substantially less than said unity gain frequency.

Claim 43

A conditionally-stable operational amplifier comprising a signal input, a signal output, a gain stage in a signal path from the signal input to the signal output, and a current feedback input, wherein the gain stage is responsive to the current feedback input to assert an output signal on the signal output in response to current received at the current feedback input, wherein the output stage asserts a voltage on the signal output in proportion to current received at the current feedback input, the conditionally-stable operational amplifier has a unity gain frequency for unity gain from said signal input to said signal output, and wherein the conditionally-stable operational amplifier has a transimpedance from the current input to the signal output that has a phase lag of more than 180 degrees from the current output to the current input for a frequency substantially less than said unity gain frequency.

Claim 44

The conditionally-stable operational amplifier as claimed in claim 36, further including at least two integrator stages in a low-frequency path from said current feedback input to said output stage, and a relatively high-frequency path from said current feedback input to said output stage for bypassing said at least two integrator stages.

Claim 45

A conditionally-stable operational amplifier comprising, in combination: a voltage signal input; at least three integrator stages connected to provide a low-frequency path from the voltage signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; a current feedback input; and a shunt resistance from the current feedback input to a signal ground, wherein the conditionally-stable operational amplifier has an open-loop gain from said voltage signal input to said signal output inversely proportional to said shunt resistance.

Claim 46

A conditionally-stable operational amplifier comprising, in combination: a voltage signal input; at least three integrator stages connected to provide a low-frequency path from the voltage signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; a current feedback input; and a shunt resistance from the current feedback input to a signal ground, wherein the conditionally-stable operational amplifier has an open-loop gain from said voltage signal input to said signal output inversely proportional to said shunt resistance.

Claim 47

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; and a current feedback input, wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented at the current feedback input; wherein the relatively high-frequency path includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current flow through the resistance presented at the current feedback input.

Claim 48

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; and a current feedback input, wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented at the current feedback input; wherein the relatively high-frequency path includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current flow through the resistance presented at the current feedback input.

Claim 49

The conditionally-stable operational amplifier as claimed in claim 39, wherein the controlled voltage source includes a differential amplifier having a feedback input connected to the current feedback input for applying to the current feedback input a voltage responsive to a difference between the input signal on the signal input and the voltage applied by the controlled voltage source to the current feedback input.

Claim 50

The conditionally-stable operational amplifier as claimed in claim 39, wherein at least one of the integrator stages are connected in the low-frequency path from the signal input to the controlled voltage source, and said at least one of the integrator stages includes a voltage feedback input substantially independent of said current feedback input.

Claim 51

The conditionally-stable operational amplifier as claimed in claim 41, further including a first feedback circuit connected from said signal output to said voltage feedback input, and a second feedback circuit connected from said signal output to said current feedback input.

Claim 52

The conditionally-stable operational amplifier as claimed in claim 42, wherein said first feedback circuit and said second feedback circuit are adjustable and are coupled for adjustment of feedback of said second feedback circuit from said signal input to said current feedback input substantially in proportion to adjustment of feedback of said first feedback circuit from said signal input to said voltage feedback input.

Claim 53

The conditionally-stable operational amplifier as claimed in claim 39, wherein the relatively high-frequency path includes a transistor follower circuit having a voltage follower output at the current feedback input.

Claim 54

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein a first one of said integrator stages has a differential amplifier including inputs that are positive and negative in polarity with respect to the signal output at zero frequency, the differential amplifier producing a difference signal responsive to a difference in voltage between the positive and negative inputs of the differential amplifier; and further including a current feedback input in the high-frequency path connected to the differential amplifier to assert a voltage on the current feedback input responsive to the difference signal of the differential amplifier; and wherein a last one of the integrator stages in the low-frequency path is responsive to current flowing from said current feedback input.

Claim 55

A conditionally-stable operational amplifier comprising, in combination: at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein a first one of said integrator stages has a differential amplifier including inputs that are positive and negative in polarity with respect to the signal output at zero frequency, the differential amplifier producing a difference signal responsive to a difference in voltage between the positive and negative inputs of the differential amplifier; and further including a current feedback input in the high-frequency path connected to the differential amplifier to assert a voltage on the current feedback input responsive to the difference signal of the differential amplifier; and wherein a last one of the integrator stages in the low-frequency path is responsive to current flowing from said current feedback input.

Claim 56

The conditionally-stable operational amplifier as claimed in claim 45, wherein the negative input of the differential amplifier is connected to the current feedback input so that the voltage on the current feedback input is proportional to a difference between voltage on the positive input of the differential amplifier and the voltage on the current feedback input.

Claim 57

The conditionally-stable operational amplifier as claimed in claim 45, further including a first feedback circuit connected from said signal output to the negative input of the differential amplifier, and a second feedback circuit connected from said signal output to said current feedback input.

Claim 58

The conditionally-stable operational amplifier as claimed in claim 47, wherein said first feedback circuit and said second feedback circuit are adjustable and are coupled for adjustment of feedback of said second feedback circuit from said signal input to said current feedback input substantially in proportion to adjustment of feedback of said first feedback circuit from said signal input to the negative input of the differential amplifier.

Claim 59

The conditionally-stable operational amplifier as claimed in claim 45, which includes a transistor follower in the relatively high-frequency bypass path, the transistor follower receiving the difference signal from the differential amplifier, having a voltage follower output at the current feedback input, and conducting current integrated by the last one of the integrator stages.

Claim 60

The conditionally-stable operational amplifier as claimed in claim 45, further including at least one intermediate integrator stage in a portion of the low-frequency path from the current feedback input to the last stage in the low-frequency path, wherein the intermediate integrator stage is bypassed by the relatively high-frequency path.

Claim 61

The conditionally-stable operational amplifier as claimed in claim 45, further including at least two intermediate integrator stages in a portion of the low-frequency path from the current feedback input to the last stage in the low-frequency path, wherein the intermediate integrator stages are bypassed by the relatively high-frequency path, and only one of the two intermediate integrator stages is further bypassed by an intermediate bypass path conveying a signal from another of the two intermediate integrator stages.

Claim 62

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the conditionally-stable operational amplifier has an open-loop unit and frequency for unity gain from said signal input to said signal output, the conditionally-stable operational amplifier has at least 180 decrees of phase lap from said signal input to said signal output for a frequency less than the open-loop unity gain frequency, and the phase lag from said signal input to said signal output decreases to less than 180 degrees as frequency increases to the open-loop unity gain frequency.

Claim 63

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the conditionally-stable operational amplifier has an open-loop unit and frequency for unity gain from said signal input to said signal output, the conditionally-stable operational amplifier has at least 180 decrees of phase lap from said signal input to said signal output for a frequency less than the open-loop unity gain frequency, and the phase lag from said signal input to said signal output decreases to less than 180 degrees as frequency increases to the open-loop unity gain frequency.

Claim 64

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the resistor feedback network is adjustable to adjust the fraction of the signal from the signal output which is applied to the negative feedback input.

Claim 65

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the resistor feedback network is adjustable to adjust the fraction of the signal from the signal output which is applied to the negative feedback input.

Claim 66

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having, a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the dynamic offset reduction circuit includes at least one chopper for chopper-stabilizing the differential amplifier.

Claim 67

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having, a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage; and wherein the dynamic offset reduction circuit includes at least one chopper for chopper-stabilizing the differential amplifier.

Claim 68

An amplifier circuit comprising in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and wherein the dynamic offset reduction circuit has a clock input for accepting at least one clock signal and produces undesirable artifacts from said clock signal, and further including an analog low-pass filter connected to the differential amplifier to prevent the undesirable artifacts from passing from the dynamic offset reduction circuit to the signal output.

Claim 69

An amplifier circuit comprising in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and wherein the dynamic offset reduction circuit has a clock input for accepting at least one clock signal and produces undesirable artifacts from said clock signal, and further including an analog low-pass filter connected to the differential amplifier to prevent the undesirable artifacts from passing from the dynamic offset reduction circuit to the signal output.

Claim 70

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and further including a bypass path from the negative feedback input to the signal output for bypassing the differential amplifier, the bypass path merging at a summing node with a low-frequency path from the differential amplifier to the signal output, the summing node combining a signal from a first signal source in the bypass path with a signal from a second signal source in the low-frequency path, the first signal source having a first saturation limit, the second signal source having a second saturation limit, and the first and second saturation limits having values so that the bypass path is not saturated when the low-frequency path saturates.

Claim 71

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and further including a bypass path from the negative feedback input to the signal output for bypassing the differential amplifier, the bypass path merging at a summing node with a low-frequency path from the differential amplifier to the signal output, the summing node combining a signal from a first signal source in the bypass path with a signal from a second signal source in the low-frequency path, the first signal source having a first saturation limit, the second signal source having a second saturation limit, and the first and second saturation limits having values so that the bypass path is not saturated when the low-frequency path saturates.

Claim 72

The amplifier circuit as claimed in claim 56, wherein the first signal source is a first current source, and the second signal source is a second current source, and the summing node combines current from the first current source with current from the second current source.

Claim 73

The amplifier circuit as claimed in claim 57, wherein the current source in the bypass path is a first differential amplifier having a common mode current having a magnitude substantially equal to the first saturation limit, and the current source in the low-frequency path is a second differential amplifier having a common mode current having a magnitude substantially equal to the second saturation limit.

Claim 74

The amplifier circuit as claimed in claim 57, wherein the current source in the bypass path is a first field-effect transistor, the current source in the low-frequency path is a second field-effect transistor, and the first field-effect transistor has a substantially higher transconductance than the second field-effect transistor.

Claim 75

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and wherein the negative feedback input is a current feedback input, and wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented by the resistor feedback network to the current feedback input.

Claim 76

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes a signal path from the signal input to the signal output including an amplifier stage having a differential amplifier for amplifying a difference between an input signal from the signal input and a feedback signal from the negative feedback input, and a dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the amplifier stage, and wherein the negative feedback input is a current feedback input, and wherein the conditionally-stable operational amplifier has an open-loop gain inversely proportional to resistance presented by the resistor feedback network to the current feedback input.

Claim 77

The amplifier circuit as claimed in claim 60, wherein the conditionally-stable operational amplifier includes a controlled voltage source applying a voltage to the current feedback input, the voltage being responsive to a signal on the signal input, and an output stage applying an output signal to the signal output in response to current flow through the resistance presented by the resistor feedback network to the current feedback input.

Claim 78

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein the low-frequency path and the relatively high-frequency path converge at a summing node combining a signal from a first signal source in the low-frequency path with a signal from a second signal source in the relatively high-frequency path, the first signal source has a first saturation limit, the second signal source has a second saturation limit, and the first and second saturation limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

Claim 79

An amplifier circuit comprising, in combination: a conditionally-stable operational amplifier having a signal input, a negative feedback input, and a signal output; and a resistor feedback network connecting the negative feedback input to the signal output for applying to the negative feedback input a fraction of a signal from the signal output; wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output; and a relatively high-frequency bypass path for bypassing at least one of the integrator stages in the low-frequency path; wherein the low-frequency path and the relatively high-frequency path converge at a summing node combining a signal from a first signal source in the low-frequency path with a signal from a second signal source in the relatively high-frequency path, the first signal source has a first saturation limit, the second signal source has a second saturation limit, and the first and second saturation limits have values so that the relatively high-frequency path is not saturated when the low-frequency path saturates.

Claim 80

The amplifier circuit as claimed in claim 62, wherein the first signal source is a first current source, and the second signal source is a second current source, and the summing node combines current from the first current source with current from the second current source.

Claim 81

The amplifier circuit as claimed in claim 63, wherein the current source in the relatively high-frequency path is a first differential amplifier having a common mode current having a magnitude substantially equal to the first saturation limit, and the current source in the low-frequency path is a second differential amplifier having a common mode current having a magnitude substantially equal to the second saturation limit.

Claim 82

The amplifier circuit as claimed in claim 63, wherein the current source in the relatively high-frequency path is a first field-effect transistor, the current source in the low-frequency path is a second field-effect transistor, and the first field-effect transistor has a substantially higher transconductance than the second field-effect transistor.

Claim 85

The method as claimed in claim 66, wherein the offset of the first one of the integrator stages is dynamically reduced by chopping the first portion of the signal before the first portion of the signal is amplified by the differential amplifier and demodulating the amplified signal before the amplified signal is passed to the next one of the integrator stages.

Claim 86

The method as claimed in claim 66, which further includes low-pass filtering the amplified signal from the differential amplifier in an analog low-pass filter to attenuate artifacts of dynamic offset reduction before the amplified and demodulated signal is received by a second one of the integrator stages.

Claim 87

The method as claimed in claim 68, which further includes attenuating the signal from the first integrator stage at zero frequency before combining the signal from the first integrator stage with the portion of the signal conveyed in the bypass path.

Claim 88

The method as claimed in claim 69, wherein the signal from the first integrator stage is combined with the portion of the signal conveyed by the bypass path to produce a combined signal received by the second one of the integrator stages.

Claim 89

The method as claimed in claim 66, wherein the signal from the first integrator stage is combined with the portion of the signal conveyed by the bypass path by converting the signal from the first integrator stage to a first current limited to a first saturation current level, converting the portion of the signal conveyed by the bypass path to a second current limited to a second saturation current level, the first and second saturation current levels having been preset so that saturation in the low-frequency path occurs before saturation in the bypass path, and summing the first current with the second current to produce a combined current signal.

Claim 90

The method as claimed in claim 66, which includes: converting at least a portion of the signal in the operational amplifier to a voltage applied to a current feedback input; producing, in a resistance connected to the current feedback input, a current substantially proportional to the voltage applied to the current feedback input; and producing, at the signal output, an output signal responsive to said current substantially proportional to the voltage applied to the current feedback input.

Claim 93

The method as claimed in claim 73, which includes: converting at least a portion of the signal in the operational amplifier to a voltage applied to a current feedback input; producing, in a resistance connected to the current feedback input, a current substantially proportional to the voltage applied to the current feedback input; and producing, at the signal output, an output signal responsive to said current substantially proportional to the voltage applied to the current feedback input.

Claim 96

The method as claimed in claim 75, wherein the current feedback input is at a location in the low-frequency path that is not bypassed by the bypass path.

Claim 97

The method as claimed in claim 75, wherein the current feedback input is at a location in the low-frequency path, said at least one integrator is in the low-frequency path between the current feedback input and the signal output, and the bypass path extends from the current feedback input and bypasses said at least one integrator in the low-frequency path between the current feedback input and the signal output.

Claim 98

The method as claimed in claim 75, wherein the voltage produced at the current feedback input is substantially proportional to a difference between the signal applied to the signal input and the voltage produced at the current feedback input.

Claim 101

The method as claimed in claim 79, wherein the ratio of the second amount of voltage feedback to the first amount of voltage feedback is substantially equal to the ratio of the second amount of current feedback to the first amount of current feedback.

Claim 102

The method as claimed in claim 79, wherein the amount of voltage feedback sets a closed-loop gain of the conditionally-stable operational amplifier, and the amount of current feedback sets an open-loop gain of the conditionally-stable operational amplifier.

Claim 103

A signal processing system comprising, in combination, a conditionally-stable operational amplifier for amplifying an analog signal to produce an amplified analog signal; a feedback network connected to the conditionally-stable operational amplifier for setting a closed-loop gain for the conditionally-stable operational amplifier; and an analog-to-digital converter for converting the amplified analog signal to a corresponding digital signal; wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output, a relatively high-frequency bypass path from the signal input to the signal output for bypassing a first one of the integrator stages in the low-frequency path, and, in the first one of the integrator stages, a differential amplifier and a dynamic offset reduction circuit responsive to a clock signal and connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages.

Claim 104

A signal processing system comprising, in combination, a conditionally-stable operational amplifier for amplifying an analog signal to produce an amplified analog signal; a feedback network connected to the conditionally-stable operational amplifier for setting a closed-loop gain for the conditionally-stable operational amplifier; and an analog-to-digital converter for converting the amplified analog signal to a corresponding digital signal; wherein the conditionally-stable operational amplifier includes at least three integrator stages connected to provide a low-frequency path from a signal input to a signal output, a relatively high-frequency bypass path from the signal input to the signal output for bypassing a first one of the integrator stages in the low-frequency path, and, in the first one of the integrator stages, a differential amplifier and a dynamic offset reduction circuit responsive to a clock signal and connected to the differential amplifier to provide a reduction in differential offset voltage of the first one of the integrator stages.

Claim 105

The signal processing system as claimed in claim 82, wherein the analog-to-digital converter is also responsive to a clock signal for controlling sampling and conversion of the amplified analog signal to produce the corresponding digital signal, and wherein the signal processing system includes a connection between the analog-to-digital converter and the conditionally-stable operational amplifier so that the dynamic offset reduction circuit operates in synchronism with the sampling and conversion by the analog-to-digital converter.

Claim 106

The signal processing system as claimed in claim 82, wherein the feedback network is adjustable for a plurality of predetermined closed-loop gain settings of the conditionally-stable operational amplifier.

Claim 107

A signal processing system for amplifying an analog differential signal including a first analog signal and a second analog signal, said system comprising, in combination: a first conditionally-stable operational amplifier for amplifying the first analog signal to produce a first amplified analog signal, the first conditionally-stable operational amplifier having a first signal input for receiving the first analog signal, a first negative feedback input, and a first signal output for providing the first amplified analog signal; a second conditionally-stable operational amplifier for amplifying the second analog signal to produce a second amplified analog signal, the second conditionally-stable operational amplifier having a second signal input for receiving the second analog signal, a second negative feedback input, and a second signal output for providing the second amplified analog signal; a resistor feedback network connected between said first signal output and said second output and having a first node connected to said first negative feedback input and a second node connected to said second negative feedback input so that said first conditionally-stable operational amplifier has a first closed-loop gain for amplifying said first analog signal and said second conditionally-stable operational amplifier has a second closed loop gain for amplifying said second analog signal, said first closed-loop gain being substantially equal to said second closed-loop gain; and an analog-to-digital converter for converting the first amplified analog signal and the second amplified analog signal to a corresponding digital signal representing a difference between the first amplified analog signal and the second amplified analog signal; wherein the first conditionally-stable operational amplifier includes a signal path from the first signal input to the first signal output including a first amplifier stage having a first differential amplifier for amplifying a difference between the first analog input signal from the first signal input and a first feedback signal from the first negative feedback input, and a first dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first amplifier stage; and wherein the second conditionally-stable operational amplifier includes a signal path from the second signal input to the second signal output including a second amplifier stage having a second differential amplifier for amplifying a difference between the second analog input signal from the second signal input and a second feedback signal from the second negative feedback input, and a second dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the second amplifier stage.

Claim 108

A signal processing system for amplifying an analog differential signal including a first analog signal and a second analog signal, said system comprising, in combination: a first conditionally-stable operational amplifier for amplifying the first analog signal to produce a first amplified analog signal, the first conditionally-stable operational amplifier having a first signal input for receiving the first analog signal, a first negative feedback input, and a first signal output for providing the first amplified analog signal; a second conditionally-stable operational amplifier for amplifying the second analog signal to produce a second amplified analog signal, the second conditionally-stable operational amplifier having a second signal input for receiving the second analog signal, a second negative feedback input, and a second signal output for providing the second amplified analog signal; a resistor feedback network connected between said first signal output and said second output and having a first node connected to said first negative feedback input and a second node connected to said second negative feedback input so that said first conditionally-stable operational amplifier has a first closed-loop gain for amplifying said first analog signal and said second conditionally-stable operational amplifier has a second closed loop gain for amplifying said second analog signal, said first closed-loop gain being substantially equal to said second closed-loop gain; and an analog-to-digital converter for converting the first amplified analog signal and the second amplified analog signal to a corresponding digital signal representing a difference between the first amplified analog signal and the second amplified analog signal; wherein the first conditionally-stable operational amplifier includes a signal path from the first signal input to the first signal output including a first amplifier stage having a first differential amplifier for amplifying a difference between the first analog input signal from the first signal input and a first feedback signal from the first negative feedback input, and a first dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the first amplifier stage; and wherein the second conditionally-stable operational amplifier includes a signal path from the second signal input to the second signal output including a second amplifier stage having a second differential amplifier for amplifying a difference between the second analog input signal from the second signal input and a second feedback signal from the second negative feedback input, and a second dynamic offset reduction circuit connected to the differential amplifier to provide a reduction in differential offset voltage of the second amplifier stage.

Claim 109

The signal processing system as claimed in claim 85, wherein the analog-to-digital converter is responsive to the clock signal for controlling sampling and conversion of the first and second amplified analog signals to produce the corresponding digital signal, and wherein the signal processing system includes a connection between the analog-to-digital converter and the first and second conditionally-stable operational amplifiers so that the dynamic offset reduction circuit operates in synchronism with the sampling and conversion by the analog-to-digital converter.

Claim 110

The signal processing system as claimed in claim 85, wherein the resistor feedback network is adjustable for a plurality of predetermined closed-loop gain settings of the first and second conditionally-stable operational amplifiers.

Claim 111

The conditionally-stable operational amplifier as claimed in claim 28, which further includes a voltage feedback input, wherein the voltage feedback input and the signal input comprise a pair of differential voltage inputs for the conditionally-stable operational amplifier.

Claim 112

The conditionally-stable operational amplifier as claimed in claim 38, which further includes a voltage feedback input, wherein the voltage feedback input and the voltage signal input comprise a pair of differential voltage inputs for the conditionally-stable operational amplifier.