Current mirror with unity gain buffer

Claim 2

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unit gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; and wherein said buffer includes means for causing a correction current to flow through said input terminal of said buffer, said correction current being responsive to the operation of said simple current mirror and in the proper sense to reduce the error current between said input terminal and said output terminal.

Claim 3

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) a first transistor having emitter, base and collector terminals; (c) unity gain buffer having input, output and feedback terminals; wherein said buffer includes means for controlling a current through said feedback terminal sensitive to a current flowing in said base of said transistor; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said feedback terminal of said buffer is connected in common to said emitter terminal of said first transistor and to said input terminal of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror.

Claim 4

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) a first transistor having emitter, base and collector terminals; (c) unity gain buffer having input, output and feedback terminals; wherein said buffer includes means for controlling a current through said feedback terminal sensitive to a current flowing in said base of said transistor; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said feedback terminal of said buffer is connected in common to said emitter terminal of said first transistor and to said input terminal of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror.

Claim 5

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; wherein said unity gain buffer comprises a second transistor and first bias means for biasing said second transistor; wherein said second transistor includes base, emitter, and collector terminals; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; and wherein said collector terminal of said second transistor is connected to said first bias means; wherein said first and second transistors are of the same polarity; further comprising second bias means which comprises (a) first and second diodes, (b) a resistor, and (c) a first voltage source; wherein said diodes and said resistor are connected in series between said first voltage source and said emitter terminal of said second transistor in a manner such that said second transistor is biased on.

Claim 6

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; wherein said unity gain buffer comprises a second transistor and first bias means for biasing said second transistor; wherein said second transistor includes base, emitter, and collector terminals; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; and wherein said collector terminal of said second transistor is connected to said first bias means; wherein said first and second transistors are of the same polarity; further comprising second bias means which comprises (a) first and second diodes, (b) a resistor, and (c) a first voltage source; wherein said diodes and said resistor are connected in series between said first voltage source and said emitter terminal of said second transistor in a manner such that said second transistor is biased on.

Claim 7

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; wherein said unity gain buffer comprises a second transistor and first bias means for biasing said second transistor; wherein said second transistor includes base, emitter, and collector terminals; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; and wherein said collector terminal of said second transistor is connected to said first bias means; and further comprising second bias means comprising (a) a resistor, (b) a voltage source, and (c) a third transistor having base, emitter and collector terminals; wherein said simple current mirror includes input and output transistors each having base, emitter and collector terminals; wherein the base terminals of said input, output, and third transistors are connected together in common with said collector terminal of said input transistor and said emitter terminal of said first transistor; wherein said collector terminal of said third transistor is connected to said emitter terminal of said second transistor; wherein said emitter terminal of said third transistor is connected in series with said resistor and said voltage source; and wherein said first, second and third transistors are of the same polarity.

Claim 8

An improved current mirror having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; wherein said unity gain buffer comprises a second transistor and first bias means for biasing said second transistor; wherein said second transistor includes base, emitter, and collector terminals; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; and wherein said collector terminal of said second transistor is connected to said first bias means; and further comprising second bias means comprising (a) a resistor, (b) a voltage source, and (c) a third transistor having base, emitter and collector terminals; wherein said simple current mirror includes input and output transistors each having base, emitter and collector terminals; wherein the base terminals of said input, output, and third transistors are connected together in common with said collector terminal of said input transistor and said emitter terminal of said first transistor; wherein said collector terminal of said third transistor is connected to said emitter terminal of said second transistor; wherein said emitter terminal of said third transistor is connected in series with said resistor and said voltage source; and wherein said first, second and third transistors are of the same polarity.

Claim 9

An improved current mirror, having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; and wherein said unit gain buffer comprises: (a) a second transistor having base, emitter and collector terminals; wherein said second transistor and said first transistor are of opposite polarity; (b) bias means for biasing said second transistor; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; wherein said collector terminal of said second transistor is connected in common with said emitter terminal of said first transistor and said input terminal of said simple current mirror; and wherein said bias means is connected to said emitter of said second transistor.

Claim 10

An improved current mirror, having input and output terminals, and further comprising: (a) a simple current mirror having input and output terminals, and a bias terminal for connection to a voltage source; (b) unity gain buffer having input and output terminals; and (c) a first transistor having emitter, base and collector terminals; wherein said input terminal of said buffer is connected in common with said output terminal of said simple current mirror to form said input terminal of said improved current mirror; wherein said output terminal of said buffer is connected to said base terminal of said first transistor; wherein said emitter terminal of said first transistor is connected to said input of said simple current mirror; and wherein said collector terminal of said first transistor comprises said output terminal of said improved current mirror; and wherein said unit gain buffer comprises: (a) a second transistor having base, emitter and collector terminals; wherein said second transistor and said first transistor are of opposite polarity; (b) bias means for biasing said second transistor; wherein said base terminal of said second transistor comprises said input terminal of said buffer; wherein said emitter terminal of said second transistor comprises said output terminal of said buffer; wherein said collector terminal of said second transistor is connected in common with said emitter terminal of said first transistor and said input terminal of said simple current mirror; and wherein said bias means is connected to said emitter of said second transistor.

Claim 11

An improved current mirror in accordance with claim 5, wherein said bias means comprises a current source.

Claim 12

An improved current mirror in accordance with claim 6, wherein said bias means further comprises a resistor connected in parallel with said current source.