Switched-capacitor integrator with chopper stabilization performed at the sampling rate

Claim 2

A switched-capacitor circuit having a sampled output comprising: a) a discrete time charge transfer circuit coupled to an input signal; b) a chopper stabilized amplifier coupled to said discrete time charge transfer circuit and to a chop clock signal; and c) a sampling circuit coupled between said chopper stabilized amplifier and said sampled output, said sampling circuit also coupled to a sampling clock signal, d) wherein said amplifier is chopped at a frequency greater than or substantially equal to the frequency that said output is sampled.

Claim 3

A switched-capacitor circuit as set forth in claim 1 wherein said switched-capacitor circuit is an integrator circuit.

Claim 4

A switched-capacitor circuit as set forth in claim 2 wherein said integrator is a double sampled integrator.

Claim 5

A switched-capacitor circuit as set forth in claim 1 wherein said switched-capacitor circuit is fully differential.

Claim 6

A switched capacitor circuit for receiving an input signal at an input terminal and for providing an output signal, comprising: a) a chopped amplifier having first and second inputs and an output and having first and second chopping states; b) a feedback capacitor coupled between said output of said amplifier and said first input of said amplifier; c) an input capacitor having a first terminal selectively coupled to said input terminal and to signal ground, and said input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said input capacitor is alternately (i) charged to a signal at said input terminal and (ii) coupled to said first input of said amplifier to thereby transfer its charge to said feedback capacitor during each chopping state of said amplifier; and e) said output of said amplifier is sampled, to provide said output signal, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 7

A switched capacitor circuit for receiving an input signal at an input terminal and for providing an output signal, comprising: a) a chopped amplifier having first and second inputs and an output and having first and second chopping states; b) a feedback capacitor coupled between said output of said amplifier and said first input of said amplifier; c) an input capacitor having a first terminal selectively coupled to said input terminal and to signal ground, and said input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said input capacitor is alternately (i) charged to a signal at said input terminal and (ii) coupled to said first input of said amplifier to thereby transfer its charge to said feedback capacitor during each chopping state of said amplifier; and e) said output of said amplifier is sampled, to provide said output signal, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 8

A switched capacitor circuit for receiving first and second input signals at first and second input terminals, respectively, and for providing first and second output signals, respectively, comprising: a) a chopped amplifier having first and second inputs and first and second outputs and having first and second chopping states; b) a first feedback capacitor coupled between said first output of said amplifier and said first input of said amplifier, and a second feedback capacitor coupled between said second output of said amplifier and said second input of said amplifier; c) a first input capacitor having a first terminal selectively coupled to said first input terminal and to said second input terminal, and said first input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said first capacitor is alternately (i) charged to a signal at said first input terminal and (ii) coupled to said first input of said amplifier and to said second input terminal to thereby transfer its charge to said first feedback capacitor during each chopping state of said amplifier; e) a second input capacitor having a first terminal selectively coupled to said first input terminal and to said second input terminal, and said second input capacitor having a second terminal selectively coupled to said second input of said amplifier and to signal ground; f) wherein said second capacitor is alternately (i) charged to a signal at said second input terminal and (ii) coupled to said second input of said amplifier and to said first input terminal to thereby transfer its charge to said second feedback capacitor during each chopping state of said amplifier; and g) said first and second outputs of said amplifier are sampled, to provide said first and second output signals, respectively, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 9

A switched capacitor circuit for receiving first and second input signals at first and second input terminals, respectively, and for providing first and second output signals, respectively, comprising: a) a chopped amplifier having first and second inputs and first and second outputs and having first and second chopping states; b) a first feedback capacitor coupled between said first output of said amplifier and said first input of said amplifier, and a second feedback capacitor coupled between said second output of said amplifier and said second input of said amplifier; c) a first input capacitor having a first terminal selectively coupled to said first input terminal and to said second input terminal, and said first input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said first capacitor is alternately (i) charged to a signal at said first input terminal and (ii) coupled to said first input of said amplifier and to said second input terminal to thereby transfer its charge to said first feedback capacitor during each chopping state of said amplifier; e) a second input capacitor having a first terminal selectively coupled to said first input terminal and to said second input terminal, and said second input capacitor having a second terminal selectively coupled to said second input of said amplifier and to signal ground; f) wherein said second capacitor is alternately (i) charged to a signal at said second input terminal and (ii) coupled to said second input of said amplifier and to said first input terminal to thereby transfer its charge to said second feedback capacitor during each chopping state of said amplifier; and g) said first and second outputs of said amplifier are sampled, to provide said first and second output signals, respectively, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 10

A switched capacitor circuit for receiving first and second input signals at first and second input terminals, respectively, and providing first and second outputs at first and second output terminals, respectively, comprising: a) a chopped amplifier having first and second inputs and first and second outputs and having first and second chopping states; b) a first feedback capacitor coupled between said first output of said amplifier and said first input of said amplifier, and a second feedback capacitor coupled between said second output of said amplifier and said second input of said amplifier; c) a first input capacitor having a first terminal selectively coupled to said first input terminal and to signal ground, and said first input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said first capacitor is alternately (i) charged to a signal at said first input terminal and (ii) coupled to said first input of said amplifier to thereby transfer its charge to said first feedback capacitor during each chopping state of said amplifier; e) a second input capacitor having a first terminal selectively coupled to said second input terminal and to signal ground, and said second input capacitor having a second terminal selectively coupled to said second input of said amplifier and to signal ground; f) wherein said second capacitor is alternately (i) charged to a signal at said second input terminal and (ii) coupled to said second input of said amplifier to thereby transfer its charge to said second feedback capacitor during each chopping state of said amplifier; and g) said first and second outputs of said amplifier are sampled, to provide said first and second output signals, respectively, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 11

A switched capacitor circuit for receiving first and second input signals at first and second input terminals, respectively, and providing first and second outputs at first and second output terminals, respectively, comprising: a) a chopped amplifier having first and second inputs and first and second outputs and having first and second chopping states; b) a first feedback capacitor coupled between said first output of said amplifier and said first input of said amplifier, and a second feedback capacitor coupled between said second output of said amplifier and said second input of said amplifier; c) a first input capacitor having a first terminal selectively coupled to said first input terminal and to signal ground, and said first input capacitor having a second terminal selectively coupled to said first input of said amplifier and to signal ground; d) wherein said first capacitor is alternately (i) charged to a signal at said first input terminal and (ii) coupled to said first input of said amplifier to thereby transfer its charge to said first feedback capacitor during each chopping state of said amplifier; e) a second input capacitor having a first terminal selectively coupled to said second input terminal and to signal ground, and said second input capacitor having a second terminal selectively coupled to said second input of said amplifier and to signal ground; f) wherein said second capacitor is alternately (i) charged to a signal at said second input terminal and (ii) coupled to said second input of said amplifier to thereby transfer its charge to said second feedback capacitor during each chopping state of said amplifier; and g) said first and second outputs of said amplifier are sampled, to provide said first and second output signals, respectively, at a frequency less than or substantially equal to the chopping frequency of said amplifier.

Claim 12

An analog filter comprising a plurality of serially coupled discrete time integrator stages having a first stage coupled to an input terminal and a last stage coupled to an output terminal in which at least one integrator stage of said integrator stages is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 13

An analog filter comprising a plurality of serially coupled discrete time integrator stages having a first stage coupled to an input terminal and a last stage coupled to an output terminal in which at least one integrator stage of said integrator stages is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 14

An analog filter as set forth in claim 8 wherein said at least one integrator stage is the first integrator stage of said plurality of serially coupled discrete time integrator stages.

Claim 15

An analog filter as set forth in claim 9 wherein said first integrator stage is a double sampled integrator.

Claim 16

A plurality of serially coupled discrete time integrators in an analog-to-digital modulator wherein a first stage of said integrators is coupled to an input terminal and a last stage of said integrators is coupled to an output terminal characterized in that at least one integrator of said integrators contains an amplifier which is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 17

A plurality of serially coupled discrete time integrators in an analog-to-digital modulator wherein a first stage of said integrators is coupled to an input terminal and a last stage of said integrators is coupled to an output terminal characterized in that at least one integrator of said integrators contains an amplifier which is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 18

A plurality of serially coupled discrete time integrators as set forth in claim 11 wherein said at least one integrator is the first integrator of said plurality of serially coupled discrete time integrator.

Claim 19

An analog-to-digital modulator including a summing circuit coupled to an analog loop filter, the output of said analog loop filter coupled to a quantizer, the output of said quantizer forming an output of said analog-to-digital modulator and also coupled to a digital-to-analog converter, the output of said digital-to-analog converter coupled to one input of said summing circuit, a second input of said summing circuit for receiving an analog input signal, wherein said analog loop filter comprises a plurality of serially coupled discrete-time integrators, the first integrator of said plurality of serially coupled discrete-time integrators is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 20

An analog-to-digital modulator including a summing circuit coupled to an analog loop filter, the output of said analog loop filter coupled to a quantizer, the output of said quantizer forming an output of said analog-to-digital modulator and also coupled to a digital-to-analog converter, the output of said digital-to-analog converter coupled to one input of said summing circuit, a second input of said summing circuit for receiving an analog input signal, wherein said analog loop filter comprises a plurality of serially coupled discrete-time integrators, the first integrator of said plurality of serially coupled discrete-time integrators is chopper stabilized at a frequency greater than or substantially equal to a sampling frequency of the remainder of said integrator stages.

Claim 21

An analog-to-digital modulator as set forth in claim 13 wherein first integrator is a double sampled integrator.

Claim 22

An amplifier having an input terminal and an output terminal, comprising: a) a first chopper stabilized circuit coupled to said input terminal of said amplifier, said first chopper stabilized circuit producing unwanted noise at a chopping frequency of said first chopper stabilized circuit; and b) a switched-capacitor circuit coupled between the output of said first chopper stabilized circuit and said output terminal, said switched-capacitor circuit having its input sampled at twice the chopping frequency of said first chopper stabilized circuit and M times an output sampling frequency of said switched-capacitor circuit, where M is a positive integer greater than or equal to two, to provide a noise transfer function which effectively attenuates said unwanted noise from said first chopper stabilized circuit.

Claim 23

An amplifier having an input terminal and an output terminal, comprising: a) a first chopper stabilized circuit coupled to said input terminal of said amplifier, said first chopper stabilized circuit producing unwanted noise at a chopping frequency of said first chopper stabilized circuit; and b) a switched-capacitor circuit coupled between the output of said first chopper stabilized circuit and said output terminal, said switched-capacitor circuit having its input sampled at twice the chopping frequency of said first chopper stabilized circuit and M times an output sampling frequency of said switched-capacitor circuit, where M is a positive integer greater than or equal to two, to provide a noise transfer function which effectively attenuates said unwanted noise from said first chopper stabilized circuit.

Claim 24

An amplifier as set forth in claim 15 wherein said switched-capacitor circuit contains a chopper stabilized amplifier which is chopped at substantially the same frequency as said first chopper stabilized circuit and at substantially the same frequency as the output sampling frequency of said switched-capacitor circuit.