US4746899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for reducing effects of electrical noise in an analog-to-digital converter
Assignee: TECHNOLOGY FUNDING SECURED INVESTORS A CA LP
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Filing: 1986-10-07
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Granted: 1988-05-24
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Expires: 2006-10-07
Abstract
Abstract Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
Inventors
- 👤 Eric J. Swanson
- 👤 Navdeep S. Sooch
- 👤 David J. Knapp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:34
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/324; H03M3/458
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
167 words
In conjunction with an integrated circuit having an analog-to-digital converter included therein, said analog-to-digital converter having both analog and digital circuitry embodied in a common semiconductor substrate, said digital circuitry being responsive to the leading edge of a slave clock signal for changing the logic states of a plurality of logic gates and thereby generating electrical noise, a method for reducing deleterious effects of said electrical noise on the analog-to-digital conversion process, said method comprising: a. providing a first clock signal to said analog circuitry for controlling the sampling of an analog input voltage; b. sampling said analog input voltage during a sampling portion of the period of said first clock signal and terminating said sampling at the trailing edge of said sampling portion of said first clock signal; c. generating a second clock signal having its leading edge delayed with respect to the trailing edge of said first clock signal; and d. providing said second clock signal to said digital circuitry as the slave clock thereof.
Claim 2
Dependent Claim
167 words
In conjunction with an integrated circuit having an analog-to-digital converter included therein, said analog-to-digital converter having both analog and digital circuitry embodied in a common semiconductor substrate, said digital circuitry being responsive to the leading edge of a slave clock signal for changing the logic states of a plurality of logic gates and thereby generating electrical noise, a method for reducing deleterious effects of said electrical noise on the analog-to-digital conversion process, said method comprising: a. providing a first clock signal to said analog circuitry for controlling the sampling of an analog input voltage; b. sampling said analog input voltage during a sampling portion of the period of said first clock signal and terminating said sampling at the trailing edge of said sampling portion of said first clock signal; c. generating a second clock signal having its leading edge delayed with respect to the trailing edge of said first clock signal; and d. providing said second clock signal to said digital circuitry as the slave clock thereof.
Claim 3
Dependent Claim
166 words
In conjunction with an integrated circuit having an analog-to-digital converter included therein, said analog-to-digital converter being of the type having an analog front-end of the oversampling type coupled to a digital decimation filter, a method for reducing deleterious effects of electrical noise coupled into the analog circuitry of said analog-to-digital converter, said electrical noise being generated by the switching action of the circuitry comprising said decimation filter, said method comprising: a. providing a slave clock signal to said decimation filter for synchronously clocking the logic circuitry comprising said decimation filter; b. reducing the number of gate delays subsequent to the leading edge of said slave clock signal by synchronously pipelining the arithmetic operations of said decimation filter; c. providing a sampling clock signal to said analog front-end; and d. sampling the analog input voltage during a sampling portion of the period of said sampling clock signal and terminating the sampling of the analog input voltage shortly prior to the leading edge of said slave clock signal.
Claim 4
Dependent Claim
166 words
In conjunction with an integrated circuit having an analog-to-digital converter included therein, said analog-to-digital converter being of the type having an analog front-end of the oversampling type coupled to a digital decimation filter, a method for reducing deleterious effects of electrical noise coupled into the analog circuitry of said analog-to-digital converter, said electrical noise being generated by the switching action of the circuitry comprising said decimation filter, said method comprising: a. providing a slave clock signal to said decimation filter for synchronously clocking the logic circuitry comprising said decimation filter; b. reducing the number of gate delays subsequent to the leading edge of said slave clock signal by synchronously pipelining the arithmetic operations of said decimation filter; c. providing a sampling clock signal to said analog front-end; and d. sampling the analog input voltage during a sampling portion of the period of said sampling clock signal and terminating the sampling of the analog input voltage shortly prior to the leading edge of said slave clock signal.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said analog circuitry comprises an analog front-end of the oversampling type.
Claim 6
Dependent Claim
17 words
The method of claim 3 wherein said analog front-end of the oversampling type comprises a delta-sigma modulator.
References Cited (Backward Citations)
US4227185A
Cited
US4495591A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |