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US5996097A
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Testing logic associated with numerous memory cells in the word or bit dimension in parallel
Assignee: International Business Machines Corp
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Filing: 1997-04-28
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Granted: 1999-11-30
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Expires: 2017-04-28
Abstract
Abstract The present invention is a system and method of testing logic circuits in memory of an integrated circuit in a fraction of the time. The present invention discloses a system and method to allow testing imbedded array logic blocks in parallel, rather than sequentially. The present invention allows for the testing of multiple logic blocks associated with different memory or column locations at the same time. This technique allows for reduction in test time by a factor of X, where X is the number of rows or columns or memory cells feeding logic.
Inventors
- 👤 Donald Evans
- 👤 Luigi Ternullo, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:28
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
105 words
A method of parallel testing a plurality of logic circuits embedded in a memory array in an integrated circuit, comprising: providing a test pattern; simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells in the memory array, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; accessing the test patterns stored in the memory cells; applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs; and comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 2
Independent Claim
105 words
A method of parallel testing a plurality of logic circuits embedded in a memory array in an integrated circuit, comprising: providing a test pattern; simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells in the memory array, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; accessing the test patterns stored in the memory cells; applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs; and comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein the memory array is a non-scannable memory.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein the array is to be selected from one of a BAT (block address translation buffer), SLB (segment lookaside buffer), or directory array.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein the plurality of logic circuits are used to mask and unmask memory cells in the memory array.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein the plurality of logic circuits are used to provide validation logic.
Claim 7
Dependent Claim
21 words
The method of claim 1, wherein scannable latches are used to write the test pattern into the plurality of logic circuits.
Claim 8
Independent Claim
122 words
A method of parallel testing a plurality of logic circuits embedded in a memory array in an integrated circuit, comprising: simultaneously turning on a plurality of word lines in the memory array; providing a test pattern; simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells associated with the plurality of word lines, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; accessing the test patterns stored in the plurality of memory cells; applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs; and comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 9
Independent Claim
122 words
A method of parallel testing a plurality of logic circuits embedded in a memory array in an integrated circuit, comprising: simultaneously turning on a plurality of word lines in the memory array; providing a test pattern; simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells associated with the plurality of word lines, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; accessing the test patterns stored in the plurality of memory cells; applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs; and comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 10
Dependent Claim
17 words
The method of claim 7, wherein the test pattern is written using a plurality of scannable latches.
Claim 11
Dependent Claim
13 words
The method of claim 7, wherein the memory array is a non-scannable array.
Claim 12
Dependent Claim
15 words
The method of claim 7, wherein the comparing step uses a plurality of observable latches.
Claim 13
Dependent Claim
16 words
The method of claim 10, wherein the observable latches store a plurality of test mode outputs.
Claim 14
Dependent Claim
19 words
The method of claim 7, wherein the plurality of word lines are turned on by a test enabling signal.
Claim 15
Dependent Claim
132 words
An integrated circuit comprising: a memory array having a plurality of logic circuits embedded therein; a system for simultaneously turning on a plurality of word lines in the memory array; a system for providing a test pattern; a system for simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells associated with the plurality of word lines, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; and a system for accessing the test patterns stored in the plurality of memory cells, for applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs, and for comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 16
Dependent Claim
132 words
An integrated circuit comprising: a memory array having a plurality of logic circuits embedded therein; a system for simultaneously turning on a plurality of word lines in the memory array; a system for providing a test pattern; a system for simultaneously writing the entire test pattern in parallel into each of a plurality of memory cells associated with the plurality of word lines, wherein the same test pattern is simultaneously written into all of the plurality of memory cells; and a system for accessing the test patterns stored in the plurality of memory cells, for applying the accessed test patterns to the logic circuits embedded in the memory array to obtain test outputs, and for comparing the test outputs to expected values to test the logic circuits embedded in the memory array.
Claim 17
Dependent Claim
15 words
The integrated circuit according to claim 13, wherein the memory array is a non-scannable memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |