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US5996068A
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Method and apparatus for renaming registers corresponding to multiple thread identifications
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-03-26
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Granted: 1999-11-30
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Expires: 2017-03-26
Abstract
Abstract A circuit and a scheme for register renaming responsive to a thread ID register, comprises: a plurality of physical registers; a plurality of architectual registers; a rename logic circuit where every write to an architectual register of the plurality of architectural registers is assigned a new physical register of the plurality of physical registers; a register map circuit containing a corresponding entry for each of the plurality of architectual registers. The register map circuit is responsive to the thread ID register such that a different physical map is selected for architectual registers of each thread, whereby the plurality of architectual registers can be greater than the plurality of physical registers.
Inventors
- 👤 Harry Dwyer, III
- 👤 Hubert Rae McLellan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3851
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
114 words
A register renaming circuit responsive to a thread ID register, comprising: a plurality of physical registers shared between multiple threads; a plurality of architectural registers; a rename logic circuit where every write to an architectural register of said plurality of architectural registers is assigned a new physical register of said plurality of physical registers; and a register map circuit comprising a plurality of maps corresponding to different thread IDs, said plurality of maps containing a corresponding entry for each of said plurality of architectural registers, said register map circuit is responsive to the thread ID register such that a subset of said plurality of physical registers is mapped to architectural registers of each thread.
Claim 2
Dependent Claim
114 words
A register renaming circuit responsive to a thread ID register, comprising: a plurality of physical registers shared between multiple threads; a plurality of architectural registers; a rename logic circuit where every write to an architectural register of said plurality of architectural registers is assigned a new physical register of said plurality of physical registers; and a register map circuit comprising a plurality of maps corresponding to different thread IDs, said plurality of maps containing a corresponding entry for each of said plurality of architectural registers, said register map circuit is responsive to the thread ID register such that a subset of said plurality of physical registers is mapped to architectural registers of each thread.
Claim 3
Dependent Claim
23 words
The circuit as recited in claim 1 wherein each of said plurality of physical registers has a free state and a mapped state.
Claim 4
Dependent Claim
29 words
The circuit as recited in claim 1 wherein said plurality of physical registers comprises a pool of physical registers wherein said physical registers being shared among said architectural registers.
Claim 5
Dependent Claim
50 words
The circuit as recited in claim 1 wherein said corresponding entry for each of said plurality of architectural registers is indicative of an invalid state or a valid state, said entry of said valid state containing an index of a physical register to which a corresponding architectural register is mapped.
Claim 6
Dependent Claim
51 words
The circuit as recited in claim 1 further comprising a register dependency comparator circuit for comparing architectural register destinations to prevent conflicting writes when multiple instructions write to a same architectural register, wherein only a last instruction to store in a particular architectural register is allocated a corresponding register map entry.
Claim 7
Dependent Claim
147 words
A register renaming circuit responsive to a thread ID register, comprising: a plurality of physical registers shared between multiple threads; a plurality of architectural registers; a rename logic circuit where every write to an architectural register of said plurality of architectural registers is assigned a new physical register of said plurality of physical registers; a register map circuit comprising a plurality of maps corresponding to different thread IDs, said plurality of maps containing a corresponding entry for each of said plurality of architectural registers, wherein said entry is indicative of an invalid state or a valid state, said entry of said valid state containing an index of a physical register to which a corresponding architectural register is mapped, said register map circuit is responsive to the thread ID register such that a subset of said plurality of physical registers is mapped to architectural registers of each thread.
Claim 8
Dependent Claim
147 words
A register renaming circuit responsive to a thread ID register, comprising: a plurality of physical registers shared between multiple threads; a plurality of architectural registers; a rename logic circuit where every write to an architectural register of said plurality of architectural registers is assigned a new physical register of said plurality of physical registers; a register map circuit comprising a plurality of maps corresponding to different thread IDs, said plurality of maps containing a corresponding entry for each of said plurality of architectural registers, wherein said entry is indicative of an invalid state or a valid state, said entry of said valid state containing an index of a physical register to which a corresponding architectural register is mapped, said register map circuit is responsive to the thread ID register such that a subset of said plurality of physical registers is mapped to architectural registers of each thread.
Claim 9
Dependent Claim
23 words
The circuit as recited in claim 6 wherein each of said plurality of physical registers has a free state and a mapped state.
Claim 10
Dependent Claim
19 words
The circuit as recited in claim 6 wherein said plurality of physical registers comprises a pool of physical registers.
Claim 11
Dependent Claim
51 words
The circuit as recited in claim 6 further comprising a register dependency comparator circuit for comparing architectural register destinations to prevent conflicting writes when multiple instructions write to a same architectural register, wherein only a last instruction to store in a particular architectural register is allocated a corresponding register map entry.
Claim 12
Independent Claim
108 words
A method of register renaming responsive to a thread ID register, comprising the steps of: assigning to an architectural register of a plurality of architectural registers on every write to said architectural register a new physical register from a plurality of physical registers shared between multiple threads; selecting a map corresponding to a thread ID from a register map circuit comprising a plurality of maps corresponding to different thread IDs mapping a subset of said plurality of physical registers to architectural registers of a thread corresponding to said selected map; and associating a corresponding entry for each of said plurality of architectural registers with a register map entry.
Claim 13
Independent Claim
108 words
A method of register renaming responsive to a thread ID register, comprising the steps of: assigning to an architectural register of a plurality of architectural registers on every write to said architectural register a new physical register from a plurality of physical registers shared between multiple threads; selecting a map corresponding to a thread ID from a register map circuit comprising a plurality of maps corresponding to different thread IDs mapping a subset of said plurality of physical registers to architectural registers of a thread corresponding to said selected map; and associating a corresponding entry for each of said plurality of architectural registers with a register map entry.
Claim 14
Dependent Claim
25 words
The method as recited in claim 10 further comprising the step of indexing said register map entry in a valid state to a physical register.
Claim 15
Dependent Claim
25 words
The method as recited in claim 10 wherein each of said plurality of physical registers is assigned either a free state or a mapped state.
Claim 16
Dependent Claim
19 words
The circuit as recited in claim 10 wherein said plurality of physical registers comprises a pool of physical registers.
Claim 17
Dependent Claim
48 words
The method as recited in claim 10 further comprising the step of comparing architectural register destinations to prevent conflicting writes when multiple instructions write to a same architectural register, wherein only a last instruction to store in a particular architectural register is allocated a particular register map entry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |