US5630149A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipelined processor with register renaming hardware to accommodate multiple size registers
Assignee: National Semiconductor Corp
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Filing: 1995-11-20
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Granted: 1997-05-13
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Expires: 2015-11-20
Abstract
Abstract A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, wherein one or more of the instructions reference a defined set of logical registers having multiple addressable sizes as sources and destinations of operands for the instruction. A plurality of physical registers are provided in excess of the number of defined set of logical registers. Physical registers are selectively allocated to one of said defined set of logical registers responsive to an instruction for writing to said one of said logical registers and the size associated with the logical register.
Inventors
- 👤 Mark Bluhm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3863; G06F9/3867
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
188 words
A microprocessor including register renaming apparatus, the microprocessor having at least one instruction pipeline with a plurality of stages for processing a stream of instructions, and having a plurality of logical registers, the stream of instructions including write instructions that when processed addressably write to a logical register having multiple addressable portions, comprising: a plurality of physical registers exceeding in number the plurality of logical registers, and register translation circuitry coupled to said at least one instruction pipeline and to said physical registers, said register translation circuitry being operable to allocate, for each of at least some of said write instructions processed, a physical register to said logical register based at least in part on which of said addressable portions of said logical register is addressed by said write instruction; wherein, for a current write instruction that is processed when a write is pending to said logical register in response to a previous write instruction, said register translation circuitry selectively allocates a new physical register to said logical register based on which of said addressable portions of said logical register are addressed by said previous and current instructions.
Claim 2
Dependent Claim
188 words
A microprocessor including register renaming apparatus, the microprocessor having at least one instruction pipeline with a plurality of stages for processing a stream of instructions, and having a plurality of logical registers, the stream of instructions including write instructions that when processed addressably write to a logical register having multiple addressable portions, comprising: a plurality of physical registers exceeding in number the plurality of logical registers, and register translation circuitry coupled to said at least one instruction pipeline and to said physical registers, said register translation circuitry being operable to allocate, for each of at least some of said write instructions processed, a physical register to said logical register based at least in part on which of said addressable portions of said logical register is addressed by said write instruction; wherein, for a current write instruction that is processed when a write is pending to said logical register in response to a previous write instruction, said register translation circuitry selectively allocates a new physical register to said logical register based on which of said addressable portions of said logical register are addressed by said previous and current instructions.
Claim 3
Dependent Claim
21 words
The microprocessor including register renaming apparatus of claim 1, wherein all of said plurality of logical registers have multiple addressable portions.
Claim 4
Dependent Claim
28 words
The microprocessor including register renaming apparatus of claim 1, wherein, the addressable portions of said logical register are selected from the group consisting of: byte, word, and doubleword.
Claim 5
Dependent Claim
37 words
The microprocessor including register renaming apparatus of claim 1, wherein the microprocessor is an x86-based microprocessor, and wherein said logical register is selected from the group consisting of: EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP.
Claim 6
Dependent Claim
31 words
The microprocessor including register renaming apparatus of claim 4, wherein, the addressable portions of said logical register is selected from the group consisting of: low byte, high byte, word, and doubleword.
Claim 7
Dependent Claim
41 words
The microprocessor including register renaming apparatus of claim 1, wherein said register translation circuitry determines whether the portion of said logical register addressed by said current write instruction encompasses the portion of said logical register addressed by said previous write instruction.
Claim 8
Dependent Claim
43 words
The microprocessor including register renaming apparatus of claim 6 wherein said register translation circuitry allocates said new physical register if the portion of said logical register addressed by said current instruction encompasses the portion of said logical register addressed by said previous instruction.
Claim 9
Dependent Claim
51 words
The microprocessor including register renaming apparatus of claim 6 wherein said register translation circuitry does not allocate said new physical register to said logical register if the portion of said logical register addressed by said current instruction does not encompasses the portion of said logical register addressed by said previous instruction.
Claim 10
Independent Claim
153 words
A method of allocating registers in a microprocessor having at least one instruction pipeline with a plurality of stages for processing a stream of instructions, and having a plurality of logical registers, the stream of instructions including write instructions that when processed addressably write to a logical register having multiple addressable portions, comprising the steps of: allocating, for each of at least some of said write instructions processed, one of a plurality of physical registers to said logical register based at least in part on which of said addressable portions of said logical register is addressed by said write instruction; and selectively allocating, for a write instruction that is processed when a write is pending to said logical register in response to a previous write instruction, a new physical register to said logical register based on which of said addressable portions of said logical register are addressed by said previous and current instructions.
Claim 11
Independent Claim
153 words
A method of allocating registers in a microprocessor having at least one instruction pipeline with a plurality of stages for processing a stream of instructions, and having a plurality of logical registers, the stream of instructions including write instructions that when processed addressably write to a logical register having multiple addressable portions, comprising the steps of: allocating, for each of at least some of said write instructions processed, one of a plurality of physical registers to said logical register based at least in part on which of said addressable portions of said logical register is addressed by said write instruction; and selectively allocating, for a write instruction that is processed when a write is pending to said logical register in response to a previous write instruction, a new physical register to said logical register based on which of said addressable portions of said logical register are addressed by said previous and current instructions.
Claim 12
Dependent Claim
17 words
The method of claim 9, wherein all of said plurality of logical registers have multiple addressable portions.
Claim 13
Dependent Claim
24 words
The method of claim 9, wherein, the addressable portions of said logical register are selected from the group consisting of: byte, word, and doubleword.
Claim 14
Dependent Claim
33 words
The method of claim 9, wherein the microprocessor is an x86-based microprocessor, and wherein said logical register is selected from the group consisting of: EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP.
Claim 15
Dependent Claim
27 words
The method of claim 12, wherein, the addressable portions of said logical register is selected from the group consisting of: low byte, high byte, word, and doubleword.
Claim 16
Dependent Claim
39 words
The method of claim 9, wherein the step of selectively allocating includes determining whether the portion of said logical register addressed by said current write instruction encompasses the portion of said logical register addressed by said previous write instruction.
Claim 17
Dependent Claim
41 words
The method of claim 14 wherein the step of selectively allocating includes allocating said new physical register if the portion of said logical register addressed by said current instruction encompasses the portion of said logical register addressed by said previous instruction.
Claim 18
Dependent Claim
48 words
The method of claim 14 wherein the step of selectively allocating includes not allocating said new physical register to said logical register if the portion of said logical register addressed by said current instruction does not encompasses the portion of said logical register addressed by said previous instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |