Patent US2200462A successfully refreshed from Google Patents.
EP0352103A2
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Pipeline bubble compression in a computer system
Assignee: Digital Equipment Corp
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Filing: 1989-07-20
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Granted: —
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Expires: 2009-07-20
Abstract
Abstract Bubble compression in a pipelined central processing unit (CPU) of a computer system is provided. A bubble represents a stage in the pipeline that cannot perform any useful work due to the lack of data from an earlier pipeline stage. When a particular pipeline stage has stalled, the CPU instructions that have already passed through this stage continue to move ahead and leave behind vacant stages or bubbles. If a bubble is introduced into a pipeline and the pipeline subsequently stalls, the disclosed CPU takes advantage of this stalled condition to compress the previously introduced bubble.
Inventors
- 👤 William R. Wheeler
- 👤 George M. Uhler
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 23:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3873; G06F9/3802; G06F9/3814; G06F9/3836
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
95 words
A method of operating a pipelined processing unit (10) in a digital computer, the pipelined processing unit having at least a first pipeline segment for processing data and a second pipeline segment for processing data downstream of the first pipeline segment; the said processing of data being capable of causing a stall condition which produces a bubble in the first pipeline segment; the method being characterised by: a) detecting a bubble in the first pipeline segment; b) thereafter detecting a stall condition in the second pipeline segment; and c) overwriting and thereby compressing the bubble.
Claim 2
Independent Claim
95 words
A method of operating a pipelined processing unit (10) in a digital computer, the pipelined processing unit having at least a first pipeline segment for processing data and a second pipeline segment for processing data downstream of the first pipeline segment; the said processing of data being capable of causing a stall condition which produces a bubble in the first pipeline segment; the method being characterised by: a) detecting a bubble in the first pipeline segment; b) thereafter detecting a stall condition in the second pipeline segment; and c) overwriting and thereby compressing the bubble.
Claim 3
Dependent Claim
27 words
A method according to Claim 1 wherein the first pipeline segment performs the operations of decoding an instruction and producing control data based upon the said instruction.
Claim 4
Dependent Claim
36 words
A method according to Claim 1 or Claim 2 wherein the second pipeline segment performs the operation of generating sets of control bits in response to the decoding of an instruction in the first pipeline segment.
Claim 5
Independent Claim
31 words
A method according to any one of the preceding claims wherein the bubble in the first segment includes a condition whereby the control data is invalid and thus may be overwriten.
Claim 6
Independent Claim
45 words
A method according to any one of the preceding claims wherein the processor includes a third pipeline segment in which operands are fetched from a register file (50), an operation is performed on the operands, and a result is stored in the register file (50).
Claim 7
Dependent Claim
20 words
A method according to Claim 5 wherein the control data includes identification of a register in the register file (50).
Claim 8
Independent Claim
33 words
A method according to any one of the preceding claims wherein the processor (10) is microprogrammed and the second pipeline segment includes fetching the sets of control bits from a microinstruction store (22)
Claim 9
Dependent Claim
147 words
A processor (10) comprising: a) a plurality of successive operating stages (fig 10), with each stage either performing some operation on a set of data or controls received from a preceding stage and passing an output set of data or controls to a succeeding stage; or introducing a stall whereby no operation is performed and no data or controls are passed to a succeeding stage, at least one of the stages then having a non-operative set of data or controls ready to be passed to a succeeding stage; b) means (44) for advancing the sets of data or controls in all of the stages simultaneously when none of the stages has introduced a stall, or in later ones of the stages downstream of a given stage when the said given stage has introduced a stall; characterised by means for overwriting the non-operative set of data or controls.
Claim 10
Dependent Claim
147 words
A processor (10) comprising: a) a plurality of successive operating stages (fig 10), with each stage either performing some operation on a set of data or controls received from a preceding stage and passing an output set of data or controls to a succeeding stage; or introducing a stall whereby no operation is performed and no data or controls are passed to a succeeding stage, at least one of the stages then having a non-operative set of data or controls ready to be passed to a succeeding stage; b) means (44) for advancing the sets of data or controls in all of the stages simultaneously when none of the stages has introduced a stall, or in later ones of the stages downstream of a given stage when the said given stage has introduced a stall; characterised by means for overwriting the non-operative set of data or controls.
Claim 11
Dependent Claim
27 words
A processor according to Claim 8 wherein the operating stages include a first stage for decoding instructions and producing control data for use in a downstream stage.
Claim 12
Dependent Claim
26 words
A processor according to Claim 9 wherein the operating stages include a second stage for generating sets of control bits in response to the decoded instructions.
Claim 13
Dependent Claim
26 words
A processor according to Claim 10 wherein the processor is microcoded and the second stage fetches the sets of control bits from a microcode store (22).
Claim 14
Dependent Claim
38 words
A processor according to Claim 9 or Claim 10 or Claim 11 wherein the sets of data or controls are temporarily stored in a latch (101, 102, 105, 107, 108), and the means for overwriting overwrites the latch.
Claim 15
Dependent Claim
36 words
A processor according to any one of Claims 8 to 12 wherein the stages include a third stage for fetching an operand from a register in a register file (50) and performing operations on the operand.
Claim 16
Dependent Claim
18 words
A processor according to Claim 13 wherein the set of data and controls includes identification of the register.
References Cited (Backward Citations)
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