US5671383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Register renaming in a superscalar microprocessor utilizing local and global renamer devices
Assignee: Intel Corp
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Filing: 1995-10-04
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Granted: 1997-09-23
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Expires: 2015-10-04
Abstract
Abstract Architectural registers for block instructions are renamed by assigning physical register locations to the architectural registers. The physical register locations are consistent with sources and destinations that are produced within a given block. The architectural registers that are renamed are then written to a current machine state. Unknown source operands of the block are renamed with physical register locations consistent with a machine state prior to the current machine state. Local renamer devices rename destination and local sources for blocks of instructions such that the destination and local sources are consistent within each block. One or more global renamers update a current machine state with the renamed block of instructions provided by the local renamers and make unknown sources in the blocks consistent with corresponding destinations from the renamed block of instructions that produced those destinations.
Inventors
- 👤 Robert Valentine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3854; G06F9/3858
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
146 words
A method of register renaming for a superscalar processor executing a program of instructions, the method comprising the steps of: (a) locally renaming register identifiers associated with first and second blocks of instructions by assigning register locations in a physical register file of the processor to the register identifiers of the first and second blocks of instructions consistent with source operands and destinations specified by the first and second blocks of instructions; (b) committing the register identifiers renamed in step (a) to the physical register file for first and second machine states of the processor, associated with the first and second blocks of instructions, respectively; (c) globally renaming unknown source operands of the locally renamed second block with register locations of the physical register file consistent with corresponding destinations of the locally renamed first block of instructions, the global renaming step producing an third machine state.
Claim 2
Independent Claim
146 words
A method of register renaming for a superscalar processor executing a program of instructions, the method comprising the steps of: (a) locally renaming register identifiers associated with first and second blocks of instructions by assigning register locations in a physical register file of the processor to the register identifiers of the first and second blocks of instructions consistent with source operands and destinations specified by the first and second blocks of instructions; (b) committing the register identifiers renamed in step (a) to the physical register file for first and second machine states of the processor, associated with the first and second blocks of instructions, respectively; (c) globally renaming unknown source operands of the locally renamed second block with register locations of the physical register file consistent with corresponding destinations of the locally renamed first block of instructions, the global renaming step producing an third machine state.
Claim 3
Dependent Claim
22 words
The method according to claim 1 further comprising the initial step of: segregating the program into the plurality of blocks of instructions.
Claim 4
Dependent Claim
21 words
The method according to claim 1 further comprising the step of: (d) repeating steps (a)-(c) for a next block of instructions.
Claim 5
Dependent Claim
31 words
The method according to claim 1 wherein the program includes multiple paths of control flow and wherein steps (a)-(c) are performed independently for each of the multiple paths of control flow.
Claim 6
Dependent Claim
95 words
A register renaming apparatus comprising: local renamer means for renaming destination and local source operands of first and second blocks of N instructions, where N is a positive integer, at first and second clock cycles, respectively, the destination and local source operands being renamed consistent within each block; global renamer means coupled to the local renamer means, the global renamer means updating a current machine state in the second cycle, or thereafter, by making unknown source operands in the locally renamed second block consistent with corresponding destinations from the locally renamed first block of instructions.
Claim 7
Dependent Claim
95 words
A register renaming apparatus comprising: local renamer means for renaming destination and local source operands of first and second blocks of N instructions, where N is a positive integer, at first and second clock cycles, respectively, the destination and local source operands being renamed consistent within each block; global renamer means coupled to the local renamer means, the global renamer means updating a current machine state in the second cycle, or thereafter, by making unknown source operands in the locally renamed second block consistent with corresponding destinations from the locally renamed first block of instructions.
Claim 8
Dependent Claim
21 words
The apparatus of claim 5 wherein the local renamer means comprises: N local renamer devices multiplexed to the global renamer means.
Claim 9
Dependent Claim
45 words
The apparatus of claim 5 wherein the local renamer means comprising N local renamer devices and the global renamer means comprises N global renamer devices, with the current machine state being passed from one global renamer device to another global renamer device per a clock.
Claim 10
Dependent Claim
43 words
The apparatus of claim 5 further comprising means for splitting the current machine state into multiple machine states corresponding to multiple paths of control flow, each of the multiple machine states being updated by an associated one of the N global renamer devices.
Claim 11
Dependent Claim
101 words
In a superscalar processor for executing a programmed flow of instructions, a method of register renaming providing a throughput of N instructions per clock comprising the steps of: (a) providing blocks of M instructions each to N/M local renamers; (b) renaming each of the blocks in consecutive clock cycles by: (i) making sources and destinations specified by the instructions of each of the blocks locally consistent; and (ii) updating a current machine state of the superscalar processor by making unknown sources specified by the instructions of each of the blocks globally consistent with corresponding destinations specified in other blocks of instructions.
Claim 12
Dependent Claim
101 words
In a superscalar processor for executing a programmed flow of instructions, a method of register renaming providing a throughput of N instructions per clock comprising the steps of: (a) providing blocks of M instructions each to N/M local renamers; (b) renaming each of the blocks in consecutive clock cycles by: (i) making sources and destinations specified by the instructions of each of the blocks locally consistent; and (ii) updating a current machine state of the superscalar processor by making unknown sources specified by the instructions of each of the blocks globally consistent with corresponding destinations specified in other blocks of instructions.
Claim 13
Dependent Claim
10 words
The method according to claim 9 wherein M equals N.
Claim 14
Dependent Claim
12 words
The method according to claim 9 wherein M is greater than N.
Claim 15
Dependent Claim
141 words
A superscalar processor having a register renaming mechanism comprising: M local renamers arranged in an ordered stack having i levels, where i is an integer that ranges from 1 to M, such that a local renamer at an ith level of the ordered stack renames sources and destinations associated with a block of N instructions to create an updated local state of the superscalar processor, the updated local state being passed to a local renamer at an (i+1)th level of the ordered stack; a global renamer coupled to the Mth local renamer for making the updated local state consistent with a current machine state of the superscalar processor by making unknown source operands associated with each of the locally renamed blocks at the Mth level consistent with corresponding destinations specified in other locally renamed blocks of instructions at the Mth level.
Claim 16
Dependent Claim
141 words
A superscalar processor having a register renaming mechanism comprising: M local renamers arranged in an ordered stack having i levels, where i is an integer that ranges from 1 to M, such that a local renamer at an ith level of the ordered stack renames sources and destinations associated with a block of N instructions to create an updated local state of the superscalar processor, the updated local state being passed to a local renamer at an (i+1)th level of the ordered stack; a global renamer coupled to the Mth local renamer for making the updated local state consistent with a current machine state of the superscalar processor by making unknown source operands associated with each of the locally renamed blocks at the Mth level consistent with corresponding destinations specified in other locally renamed blocks of instructions at the Mth level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |