US5985765A
Expired / Lapsed
US
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Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-05-11
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Granted: 1999-11-16
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Expires: 2018-05-11
Abstract
Abstract A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.
Inventors
- 👤 Yung-Kuan Hsiao
- 👤 Cheng-Ming Wu
- 👤 Yu-Hua Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:38
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W72/01; H10W72/019; H10W72/01908; H10W72/50; H10W72/59; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
205 words
A method for fabricating bonding pads for integrated circuits comprising the steps of: providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices; depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs; depositing a capping layer over said bond-pad conducting layer to provide an etch-stop layer; patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits; depositing a passivation layer over said bonding pads; selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses; selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.
Claim 2
Independent Claim
205 words
A method for fabricating bonding pads for integrated circuits comprising the steps of: providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices; depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs; depositing a capping layer over said bond-pad conducting layer to provide an etch-stop layer; patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits; depositing a passivation layer over said bonding pads; selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses; selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein said patterned conducting layers of said multilevel are composed of a metal.
Claim 4
Dependent Claim
12 words
The method of claim 2, wherein said metal is aluminum/copper (AlCu) alloy.
Claim 5
Dependent Claim
15 words
The method of claim 1, wherein said insulating layers of said multilevel are silicon oxide.
Claim 6
Dependent Claim
56 words
The method of claim 1, wherein said bond-pad conducting layer is composed of a titanium nitride layer, an aluminum copper layer, and a titanium nitride layer, where said titanium nitride layers have a thickness of between about 500 and 1500 Angstroms, and said aluminum copper layer has a thickness of between about 6000 and 10000 Angstroms.
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said capping layer is tungsten, and has a thickness of between about 500 and 2000 Angstroms.
Claim 8
Dependent Claim
34 words
The method of claim 1, wherein said passivation layer is composed of silicon nitride, a spin-on glass (SOG), and silicon oxynitride, and is deposited to a thickness of between about 6000 and 12000 Angstroms.
Claim 9
Dependent Claim
64 words
The method of claim 1, wherein said selective etching of said contact openings and said fuse openings is carried out using high-density plasma etching and an etchant gas mixture of carbon tetrafluoride, trifluoromethane, and argon, and said selective etching has an etch-rate ratio of said passivation layer and said insulating layers to said capping layer sufficiently high to prevent etching into said bonding pads.
Claim 10
Dependent Claim
39 words
The method of claim 1, wherein said capping layer exposed in said contact openings is selectively etched to expose said bonding pads while essentially leaving unetched said portions of said insulating layers in said fuse openings over said fuses.
Claim 11
Dependent Claim
30 words
The method of claim 9, wherein said etching of said bonding pads is carried out using high-density plasma etching and an etchant gas mixture of chlorine, boron trichloride, and argon.
Claim 12
Independent Claim
208 words
A method for fabricating bonding pads for integrated circuits comprising the steps of: providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices; depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs; depositing a capping layer composed of tungsten over said bond-pad conducting layer to provide an etch-stop layer; patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits; depositing a passivation layer over said bonding pads; selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses; selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.
Claim 13
Independent Claim
208 words
A method for fabricating bonding pads for integrated circuits comprising the steps of: providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices; depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs; depositing a capping layer composed of tungsten over said bond-pad conducting layer to provide an etch-stop layer; patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits; depositing a passivation layer over said bonding pads; selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses; selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.
Claim 14
Dependent Claim
18 words
The method of claim 11, wherein said patterned conducting layers of said multilevel are composed of a metal.
Claim 15
Dependent Claim
12 words
The method of claim 12, wherein said metal is aluminum/copper (AlCu) alloy.
Claim 16
Dependent Claim
15 words
The method of claim 11, wherein said insulating layers of said multilevel are silicon oxide.
Claim 17
Dependent Claim
56 words
The method of claim 11, wherein said bond-pad conducting layer is composed of a titanium nitride layer, an aluminum copper layer, and a titanium nitride layer, where said titanium nitride layers have a thickness of between about 500 and 1500 Angstroms, and said aluminum copper layer has a thickness of between about 6000 and 10000 Angstroms.
Claim 18
Dependent Claim
37 words
The method of claim 11, wherein said tungsten is deposited by chemical vapor deposition using a reactant gas of tungsten hexafluoride, and where said tungsten is deposited to a thickness of between about 500 and 2000 Angstroms.
Claim 19
Dependent Claim
34 words
The method of claim 11, wherein said passivation layer is composed of silicon nitride, a spin-on glass (SOG), and silicon oxynitride, and is deposited to a thickness of between about 6000 and 12000 Angstroms.
Claim 20
Dependent Claim
64 words
The method of claim 11, wherein said selective etching of said contact openings and said fuse openings is carried out using high-density plasma etching and an etchant gas mixture of carbon tetrafluoride, trifluoromethane, and argon, and said selective etching has an etch-rate ratio of said passivation layer and said insulating layers to said capping layer sufficiently high to prevent etching into said bonding pads.
Claim 21
Dependent Claim
39 words
The method of claim 11, wherein said capping layer exposed in said contact openings is selectively etched to expose said bonding pads while essentially leaving unetched said portions of said insulating layers in said fuse openings over said fuses.
Claim 22
Dependent Claim
30 words
The method of claim 19, wherein said etching of said bonding pads is carried out using high-density plasma etching and an etchant gas mixture of chlorine, boron trichloride, and argon.
References Cited (Backward Citations)
US5716218A
Cited
US5290588A
Cited
US5403777A
Cited
US5384284A
Cited
US5789303A
Cited
US5705428A
Cited
US5821160A
Cited
US5891808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |