Patent US5985716A successfully refreshed from Google Patents.
US5985716A
Expired / Lapsed
US
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Method for manufacturing a semiconductor device
Assignee: Rohm Co Ltd
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Filing: 1996-09-20
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Granted: 1999-11-16
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Expires: 2016-09-20
Abstract
Abstract A polysilicon layer 38 located upward of a local oxidation of silicon (LOCOS) layer 20 is removed partially when selective etching of the polysilicon layer 38 for forming a floating gate FG is carried out by carrying out anisotropic etching. The etching is stopped when only the polysilicon layer 38 is removed. Wet-etching usually carried out at the final phase of the anisotropic etching process is not performed. In this way, the LOCOS layer 20 located underneath the polysilicon layer 38 is not over-etched. As a result, an inter layer 34 is not formed in a shape of eaves on the LOCOS layer 20 when the inter layer 34 is formed. Therefore, the probability of causing stringers underneath the inter layer 34 is remarkably low.
Inventors
- 👤 Noriyuki Shimoji
- 👤 Masataka Tsuruta
- 👤 Takuya Yonezawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:17
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/35; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
146 words
A method for manufacturing a semiconductor device, said method forming first and second layers on a substrate such that an etchant used etches the second layer at a lower rate than the first layer said method comprising the steps of: a step for preparing the substrate, a step for forming the first layer on the substrate, a step for forming the second layer on the first layer, a step for carrying out selective etching with said etchant to a part of the second layer, a step for forming a conductive layer upward of the second layer, and a step for carrying out selective etching to a part of the conductive layer corresponding to the part of the second layer which was etched selectively, characterized in that, conditions for carrying out selective etching to the second layer are determined so that the first layer is not etched.
Claim 2
Independent Claim
146 words
A method for manufacturing a semiconductor device, said method forming first and second layers on a substrate such that an etchant used etches the second layer at a lower rate than the first layer said method comprising the steps of: a step for preparing the substrate, a step for forming the first layer on the substrate, a step for forming the second layer on the first layer, a step for carrying out selective etching with said etchant to a part of the second layer, a step for forming a conductive layer upward of the second layer, and a step for carrying out selective etching to a part of the conductive layer corresponding to the part of the second layer which was etched selectively, characterized in that, conditions for carrying out selective etching to the second layer are determined so that the first layer is not etched.
Claim 3
Dependent Claim
84 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the second layer has a tendency to form a silicon oxidation layer easier on the surface of the second layer than formation of the silicon oxidation layer on the surface of the first layer, and wherein a third layer is formed upward of the second layer by growing the silicon oxidation layer prior to forming the conductive layer, and after carrying out selective etching to a part of the second layer.
Claim 4
Dependent Claim
39 words
A method for manufacturing a semiconductor device in accordance, with claim 2, wherein the first layer is a layer made of silicon oxide, and wherein the second layer is a layer made of a conductive material which contains silicon.
Claim 5
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 3, wherein the second layer is made of polysilicon.
Claim 6
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 3, wherein the second layer is made of silicide.
Claim 7
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 3, wherein the second layer is made of poly-cide.
Claim 8
Dependent Claim
23 words
A method for manufacturing a semiconductor device in accordance with claim 2, wherein the second layer is made of an aluminum wiring layer.
Claim 9
Dependent Claim
23 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the second layer is either an insulator or a semiconductor.
Claim 10
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the conductive layer is made of polysilicon.
Claim 11
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the conductive layer is made of silicide.
Claim 12
Dependent Claim
20 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the conductive layer is made of polycide.
Claim 13
Dependent Claim
23 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the conductive layer is made of an aluminum wiring layer.
Claim 14
Dependent Claim
78 words
A method for manufacturing a semiconductor device in accordance with claim 1, wherein the step for carrying out selective etching to a part of the second layer is defined as the anisotropic etching process, and wherein the anisotropic etching process is composed so as not to carry out etching to the first layer by omitting wet-etching performed at the last phase of the anisotropic etching process, with carrying out selective etching of a part of the second layer.
Claim 15
Independent Claim
269 words
A method for manufacturing a semiconductor device having a plurality of elements arranged in a matrix configuration consisting of rows and columns, the device comprising: a semiconductor substrate, a lower insulation layer, a lower conductive layer such that an etchant used etches the lower conductive layer at a lower rate of etching than the lower insulation layer, said lower conductive layer having a higher rate of formation of oxidation layers than the lower insulation layer, an upper insulation layer formed by a silicon oxidation layer, and an upper conductive layer, wherein each element is formed by accumulating the lower insulation layer, the lower conductive layer, the upper insulation layer and the upper conductive layer in that order on the semiconductor substrate, and wherein each of the columns of the matrix is electrically separated from each other by a silicon oxidation layer for element separation, and wherein the upper conductive layer of the device composing a same row connects across the silicon oxidation layer for element separation, and wherein each of the upper conductive layers belonging to different rows are electrically separated from each other, characterized in that, the method comprising the steps of: a step for forming the lower insulation layer and the lower conductive layer on the semiconductor substrate, a step for removing only the lower conductive layer partially by carrying out etching with said etchant, a step for forming the upper insulation layer by growing the silicon oxidation layer, a step for forming the upper conductive layer upward of the upper insulation layer, and a step for removing the upper conductive layer partially by carrying out etching.
Claim 16
Independent Claim
269 words
A method for manufacturing a semiconductor device having a plurality of elements arranged in a matrix configuration consisting of rows and columns, the device comprising: a semiconductor substrate, a lower insulation layer, a lower conductive layer such that an etchant used etches the lower conductive layer at a lower rate of etching than the lower insulation layer, said lower conductive layer having a higher rate of formation of oxidation layers than the lower insulation layer, an upper insulation layer formed by a silicon oxidation layer, and an upper conductive layer, wherein each element is formed by accumulating the lower insulation layer, the lower conductive layer, the upper insulation layer and the upper conductive layer in that order on the semiconductor substrate, and wherein each of the columns of the matrix is electrically separated from each other by a silicon oxidation layer for element separation, and wherein the upper conductive layer of the device composing a same row connects across the silicon oxidation layer for element separation, and wherein each of the upper conductive layers belonging to different rows are electrically separated from each other, characterized in that, the method comprising the steps of: a step for forming the lower insulation layer and the lower conductive layer on the semiconductor substrate, a step for removing only the lower conductive layer partially by carrying out etching with said etchant, a step for forming the upper insulation layer by growing the silicon oxidation layer, a step for forming the upper conductive layer upward of the upper insulation layer, and a step for removing the upper conductive layer partially by carrying out etching.
Claim 17
Dependent Claim
22 words
A method for manufacturing a semiconductor device in accordance with claim 14, wherein the lower insulation layer is made of silicon oxide.
Claim 18
Dependent Claim
43 words
A method for manufacturing a semiconductor device in accordance with claim 15, wherein a gate oxidation layer is formed as the lower insulation layer, and wherein a local oxidation of silicon (LOCOS) layer is formed as the silicon oxidation layer for separating elements.
Claim 19
Dependent Claim
21 words
A method for manufacturing a semiconductor device in accordance with claim 15, wherein the lower conductive layer is made of polysilicon.
Claim 20
Dependent Claim
21 words
A method for manufacturing a semiconductor device in accordance with claim 14, wherein the upper conductive layer is made of polysilicon.
Claim 21
Dependent Claim
79 words
A method for manufacturing a semiconductor device in accordance with claim 14, wherein the step for removing only the lower conductive layer partially by carrying out etching is defined as the anisotropic etching process, and wherein the anisotropic etching process is composed so as not to carry out etching to the lower insulation layer by omitting wet-etching performed at the last phase of anisotropic etching process, while carrying out selective etching of a part of the lower conductive layer.
Claim 22
Dependent Claim
61 words
A method for manufacturing a semiconductor device in accordance with claim 14, wherein the element is a switching element having a transistor comprising: a gate oxidation layer corresponding to the lower insulation layer, a floating gate corresponding to the lower conductive layer, an inter layer corresponding to the upper insulation layer, and a control gate corresponding to the upper conductive layer.
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