US5336628A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor memory device
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1993-04-13
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Granted: 1994-08-09
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Expires: 2013-04-13
Abstract
Abstract An improved integrated circuit and fabrication method for forming the improved integrated circuit is described. The method includes an anisotropic etching, without the use of either masks or photolithography, which removes insulating material from contact openings, but keeps insulating material on the sides of conductive layers, preventing inadvertent short circuits from the contact openings to the conductive layers. The maskless etching method makes it possible to avoid mask-wafer alignment errors and therefore frees designers to perfectly center contact openings within insulative regions without taking into account the surface area tolerances required under prior art fabrication methods. This freedom allows designers to design more highly integrated devices. The particular embodiments of the semiconductor integrated circuit may include floating gates (47) and control gates (52) covered with an upper oxide layer (53) on which electrical connection lines (11) have been installed.
Inventors
- 👤 Joel Hartmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:45
CPC Classifications
H; H10; H10B; H10B69/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
224 words
A method for producing an integrated circuit comprising the steps in sequence of: a. providing a semiconductor substrate and defining active areas by establishing outside these active areas insulating zones of field oxide in an upper face of a semiconductor substrate; b. forming a first insulating layer on the upper surface of the substrate; c. depositing a conductive layer; d. depositing a second insulating layer on the conductive layer; e. patterning the second insulating layer and the conductive layer down to the first insulating layer so as to create conductive strips having reduced areas, said strips being separated by intervals having enlarged parts at locations corresponding to said reduced areas, these conductive strips forming control gates of the circuit; f. creating source and drain regions in the active areas in said intervals; g. depositing a third insulating layer to completely cover the structure produced at step (f) and completely refill the intervals outside the enlarged parts; h. masklessly anisotropically etching the third insulating layer and the first insulating layer down to the substrate to create contact openings in the enlarged parts of the intervals but leaving unaffected the refilling of the intervals by the third insulating layer outside the enlarged parts, the second insulating layer still covering the circuit outside the contact openings; and i. forming electrical connection lines extending into the contact openings.
Claim 2
Independent Claim
224 words
A method for producing an integrated circuit comprising the steps in sequence of: a. providing a semiconductor substrate and defining active areas by establishing outside these active areas insulating zones of field oxide in an upper face of a semiconductor substrate; b. forming a first insulating layer on the upper surface of the substrate; c. depositing a conductive layer; d. depositing a second insulating layer on the conductive layer; e. patterning the second insulating layer and the conductive layer down to the first insulating layer so as to create conductive strips having reduced areas, said strips being separated by intervals having enlarged parts at locations corresponding to said reduced areas, these conductive strips forming control gates of the circuit; f. creating source and drain regions in the active areas in said intervals; g. depositing a third insulating layer to completely cover the structure produced at step (f) and completely refill the intervals outside the enlarged parts; h. masklessly anisotropically etching the third insulating layer and the first insulating layer down to the substrate to create contact openings in the enlarged parts of the intervals but leaving unaffected the refilling of the intervals by the third insulating layer outside the enlarged parts, the second insulating layer still covering the circuit outside the contact openings; and i. forming electrical connection lines extending into the contact openings.
Claim 3
Dependent Claim
89 words
A method according to claim 1, and further including the steps after step b of: a. depositing a lower conductive layer on the first insulating layer; b. etching the lower conductive layer above the insulating zones; and c. forming an intermediate insulating layer above the etched lower conductive layer, the lower conductive layer and the intermediate insulating then being etched at step e together with the conductive layer deposited in step c and the second insulating layer, the etched lower conductive layer creating floating gates of the nonvolatile memory.
Claim 4
Dependent Claim
35 words
A method according to claim 1, wherein the substrate is made of silicon, and the insulting zones are formed by a localized thermal oxidation of the substrate between the active areas protected by a mask.
Claim 5
Dependent Claim
19 words
A method according to claim 1, and further including the step of doping the substrate between the insulating zones.
Claim 6
Dependent Claim
20 words
A method according to claim 1, wherein the electrical connections are formed by deposition and etching of a metallic layer.
Claim 7
Dependent Claim
17 words
A method according to claim 1, and further including the step of planarizing of the insulating zones.
Claim 8
Dependent Claim
39 words
A method according to claim 1, wherein the insulating zones are patterned in strip-form at step a, then etched after step e down to the substrate in the active areas corresponding to the sources created at subsequent step f.
Claim 9
Dependent Claim
43 words
A method according to claim 2, and further including the steps after etching the lower conductive layer, of depositing of a fourth insulating layer and etching back this fourth insulating layer down to the lower conductive layer, before depositing the intermediate insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |