Method for fabricating a non-volatile semiconductor memory device having storage cell array and peripheral circuit, and a structure therefore

Claim 1

A method of fabricating a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit on a semiconductor substrate with a field oxide layer formed thereon, said substrate provided with a peripheral circuit area and a storage cell area having a plurality of word-lines and bit-lines forming an array, said method comprising the steps of: forming a first insulation layer and a first conductive layer on a top surface of said substrate, wherein the first conductive layer is selectively etched on a selected exposed area by using a first mask pattern disposed in parallel to a first direction of said word-lines and extending in a second direction of the bit-lines; forming an oxide-nitride-oxide insulation layer by sequentially forming a lower oxide layer, a nitride layer and an upper oxide layer on the top surface of said substrate; forming a second insulation layer after exposing said peripheral circuit area by etching the oxide-nitride-oxide insulation layer and the first insulation layer formed over said peripheral circuit area; forming a second conductive layer on the top surface of said substrate; forming a floating gate and a control gate and a oxide-nitride-oxide intermediate insulation layer in contact with the floating gate and the control gate of said storage cell area by selectively etching the first conductive layer, the oxide-nitride-oxide insulation layer and the second conductive layer on a selected exposed area of said storage cell area by using a second mask pattern disposed in parallel to said first direction of said bit lines and extending in the second direction of said word-lines; and forming a transistor gate on said peripheral circuit area by selectively etching only the second conductive layer in said peripheral circuit area.

Claim 2

A method of fabricating a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit on a semiconductor substrate with a field oxide layer formed thereon, said substrate provided with a peripheral circuit area and a storage cell area having a plurality of word-lines and bit-lines forming an array, said method comprising the steps of: forming a first insulation layer and a first conductive layer on a top surface of said substrate, wherein the first conductive layer is selectively etched on a selected exposed area by using a first mask pattern disposed in parallel to a first direction of said word-lines and extending in a second direction of the bit-lines; forming an oxide-nitride-oxide insulation layer by sequentially forming a lower oxide layer, a nitride layer and an upper oxide layer on the top surface of said substrate; forming a second insulation layer after exposing said peripheral circuit area by etching the oxide-nitride-oxide insulation layer and the first insulation layer formed over said peripheral circuit area; forming a second conductive layer on the top surface of said substrate; forming a floating gate and a control gate and a oxide-nitride-oxide intermediate insulation layer in contact with the floating gate and the control gate of said storage cell area by selectively etching the first conductive layer, the oxide-nitride-oxide insulation layer and the second conductive layer on a selected exposed area of said storage cell area by using a second mask pattern disposed in parallel to said first direction of said bit lines and extending in the second direction of said word-lines; and forming a transistor gate on said peripheral circuit area by selectively etching only the second conductive layer in said peripheral circuit area.